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Datasheet File OCR Text:

STR91xFAx32 STR91XFAX42 STR91xFAx44
ARM966E-STM 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA
Features
16/32-bit 96 MHz ARM9E based MCU - ARM966E-S RISC core: Harvard architecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash) - STR91xFA implementation of core adds high-speed burst Flash memory interface, instruction prefetch queue, branch cache - Up to 96 MIPS directly from Flash memory - Single-cycle DSP instructions supported - Binary compatible with ARM7 code Dual burst Flash memories, 32-bits wide - 256 KB/512 KB Main Flash - 32 KB Secondary Flash - Sequential Burst operation up to 96 MHz - 100 K min erase cycles, 20 yr min retention SRAM, 32-bits wide - 64K or 96K bytes, optional battery backup 9 programmable DMA channels Clock, reset, and supply management - Internal oscillator operating with external 4-25 MHz crystal - Internal PLL up to 96 MHz - Real-time clock provides calendar functions, tamper, and wake-up functions - Reset Supervisor monitors supply voltage, watchdog, wake-up unit, external reset - Brown-out monitor for early warning interrupt - Run, Idle, and Sleep Mode as low as 50 uA Operating temperature -40 to +85C Vectored interrupt controller (VIC) - 32 IRQ vectors, 30 interrupt pins - Branch cache minimizes interrupt latency 8-channel, 10-bit A/D converter (ADC) - 0 to 3.6V range, 0.7 usec conversion - DMA capability
LQFP80 12 x12mm
LQFP128 14 x 14mm
LFBGA144 10 x 10 x 1.7
10 Communication interfaces - 10/100 Ethernet MAC with DMA and MII - USB Full-speed (12 Mbps) slave device - CAN interface (2.0B Active) - 3 16550-style UARTs with IrDA protocol - 2 Fast I2CTM, 400 kHz - 2 channels for SPITM, SSITM, or MicrowireTM External Memory Interface (EMI) - 8- or 16-bit data, up to 24-bit addressing - Static Async modes for LQFP128 - Additional burst synchronous modes for LFBGA144 Up to 80 I/O pins (muxed with interfaces) 16-bit standard timers (TIM) - 4 timers each with 2 input capture, 2 output compare, PWM and pulse count modes 3-Phase induction motor controller (IMC) JTAG interface with boundary scan Embedded trace module (ARM ETM9) Device summary
Root part number STR910FAM32, STR910FAW32, STR910FAZ32 STR911FAM42, STR911FAW42, STR912FAW42, STR912FAZ42 STR911FAM44 STR911FAW44 STR912FAW44, STR912FAZ44

Table 1.
Reference
STR91xFAx32 STR91XFAX42 STR91xFAx44
November 2007
Rev 2
1/99
www.st.com 1
Contents
STR91xFAx32 STR91XFAX42 STR91xFAx44
Contents
1 2 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 3.2 3.3 3.4 System-in-a-Package (SiP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ARM966E-S CPU core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Burst Flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4.1 3.4.2 3.4.3 Pre-Fetch Queue (PFQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Branch Cache (BC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Management of literals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5
SRAM (64K or 96K Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.1 3.5.2 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 3.7
DMA data movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Non-volatile memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7.1 3.7.2 Primary Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Secondary Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8 3.9
One-time-programmable (OTP) memory . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8.1 Product ID and revision level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Vectored interrupt controller (VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.9.1 3.9.2 3.9.3 FIQ handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 IRQ handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10
Clock control unit (CCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10.1 3.10.2 3.10.3 3.10.4 3.10.5 3.10.6 3.10.7 Master clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Reference clock (RCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 AHB clock (HCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 APB clock (PCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Flash memory interface clock (FMICLK) . . . . . . . . . . . . . . . . . . . . . . . . 21 Baud rate clock (BRCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 External memory interface bus clock (BCLK) . . . . . . . . . . . . . . . . . . . . 22
2/99
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Contents
USB interface clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Ethernet MAC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.10.10 External RTC calibration clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.10.11 Operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11
Flexible power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.11.1 3.11.2 3.11.3 Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.12
Voltage supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.12.1 3.12.2 Independent A/D converter supply and reference voltage . . . . . . . . . . . 24 Battery supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.13
System supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.13.1 3.13.2 3.13.3 3.13.4 3.13.5 3.13.6 3.13.7 Supply voltage brownout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Supply voltage dropout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 External RESET_INn pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 JTAG debug command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.14 3.15
Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.15.1 3.15.2 3.15.3 3.15.4 In-system-programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 CPU debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 JTAG security bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16 3.17 3.18
Embedded trace module (ARM ETM9, v. r2p2) . . . . . . . . . . . . . . . . . . . . 29 Ethernet MAC interface with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 USB 2.0 slave device interface with DMA . . . . . . . . . . . . . . . . . . . . . . . . 30
3.18.1 3.18.2 3.18.3 Packet buffer interface (PBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.19 3.20 3.21
CAN 2.0B interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 UART interfaces with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.20.1 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
I2C interfaces with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.21.1 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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3.22 3.23 3.24 3.25 3.26 3.27
SSP interfaces (SPI, SSI, and Microwire) with DMA . . . . . . . . . . . . . . . . 33
3.22.1 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
General purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 A/D converter (ADC) with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.24.1 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Standard timers (TIM) with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.25.1 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Three-phase induction motor controller (IMC) . . . . . . . . . . . . . . . . . . . . . 36 External memory interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4 5
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.1 5.2 LFBGA144 ball connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Default pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.2.1 General notes on pin usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1 6.2 6.3 6.4 Buffered and non-buffered writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 System (AHB) and peripheral (APB) buses . . . . . . . . . . . . . . . . . . . . . . . 53 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Two independent Flash memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.4.1 6.4.2 Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Optional configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.5
STR91xFA memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.2 7.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7.3.1 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 60
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7.4 7.5 7.6 7.7
RESET_INn and power-on-reset characteristics . . . . . . . . . . . . . . . . . . . 61 LVD electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.5.1 LVD delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.7.1 7.7.2 7.7.3 7.7.4 Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 65 X1_CPU external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 RTC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 66 PLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.8
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.8.1 7.8.2 SRAM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.9
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7.9.1 7.9.2 7.9.3 7.9.4 7.9.5 7.9.6 7.9.7 Functional EMS (electro magnetic susceptibility) . . . . . . . . . . . . . . . . . 69 Electro magnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 70 Electro-static discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Static latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Designing hardened software to avoid noise problems . . . . . . . . . . . . . 70 Electrical sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.10 7.11
I/O characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 External memory bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.11.1 7.11.2 Asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.12
Communication interface electrical characteristics . . . . . . . . . . . . . . . . . 81
7.12.1 7.12.2 7.12.3 7.12.4 7.12.5 10/100 Ethernet MAC electrical characteristics . . . . . . . . . . . . . . . . . . . 81 USB electrical interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 83 CAN interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 83 I2C electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 SPI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.13
ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8 9
Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
9.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
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9.2
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
10 11
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
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List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STR910/STR911 Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 STR912 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Sectoring of primary Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Sectoring of secondary Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Product ID and revision level values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VIC IRQ Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 STR91x LFBGA144 Ball Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 RESET_INn and power-on-reset characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 LVD electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Internal clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 RTC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 RTC crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 PLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 SRAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Flash memory program/erase characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Flash memory endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 ESD data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Static latch-up data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 I/O characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 EMI bus clock period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 EMI read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Mux write times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Mux read times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Page mode read times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Sync burst write times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Sync burst read times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 MII_RX_CLK and MII_TX_CLK timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 MDC timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Ethernet MII management timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Ethernet MII transmit timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Ethernet MII receive timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 I2C electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 SPI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 General ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 ADC conversion time (silicon Rev H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 ADC conversion time (silicon Rev G and lower) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
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List of tables Table 51. Table 52.
STR91xFAx32 STR91XFAX42 STR91xFAx44
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
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List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. STR91xFA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 JTAG chaining inside the STR91xFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 EMI 16-bit multiplexed connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 EMI 8-bit multiplexed connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 EMI 8-bit non-multiplexed connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 STR91xFAM 80-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 STR91xFAW 128-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 STR91xFA memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 LVD reset delay case 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 LVD reset delay case 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 LVD reset delay case 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Sleep mode current vs temperature with LVD on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Non-mux write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Non-mux bus read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Mux write diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Mux read diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Page mode read diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Sync burst write diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Sync burst read diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 MII_RX_CLK and MII_TX_CLK timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 MDC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Ethernet MII management timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Ethernet MII transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Ethernet MII receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 SPI slave timing diagram with CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 SPI slave timing diagram with CPHA=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 SPI master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Device marking for revision G LQFP80 and LQFP128 packages. . . . . . . . . . . . . . . . . . . . 90 Device marking for revision G LFBGA144 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Device marking for revision H LQFP80 and LQFP128 packages. . . . . . . . . . . . . . . . . . . . 90 Device marking for revision H LFBGA144 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 80-Pin low profile quad flat package (LQFP80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 128-Pin low profile quad flat package (LQFP128) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 144-ball low profile fine pitch ball grid array package (LFBGA144) . . . . . . . . . . . . . . . . . . 93 Recommended PCB Design rules (0.80/0.75mm pitch BGA). . . . . . . . . . . . . . . . . . . . . . . 93
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Description
STR91xFAx32 STR91XFAX42 STR91xFAx44
1
Description
STR91xFA is a series of ARM-powered microcontrollers which combines a 16/32-bit ARM966E-S RISC processor core, dual-bank Flash memory, large SRAM for data or code, and a rich peripheral set to form an ideal embedded controller for a wide variety of applications such as point-of-sale terminals, industrial automation, security and surveillance, vending machines, communication gateways, serial protocol conversion, and medical equipment. The ARM966E-S core can perform single-cycle DSP instructions, good for speech processing, audio algorithms, and low-end imaging. This datasheet provides STR91xFA ordering information, functional overview, mechanical information, and electrical device characteristics. For complete information on STR91xFA memory, registers, and peripherals, please refer to the STR91xFA Reference Manual.
For information on programming the STR91xFA Flash memory please refer to the STR9 Flash Programming Reference Manual For information on the ARM966E-S core, please refer to the ARM966E-S Rev. 2 Technical Reference Manual.
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Device summary
2
Device summary
Table 2.
Features M32X6 W32X6 Flash Kbytes RAM Kbytes Peripheral functions Packages CAN, 40 I/Os LQFP 80 256+32 64 CAN, EMI, 80 I/Os LQFP 128 LFBGA 144 USB, CAN, 40 I/Os LQFP80 Z32H6 M42X6 256+32 M44X6 512+32 96 USB, CAN, EMI, 80 I/Os LQFP128 W42X6 256 +32 W44X6 512 +32
STR910/STR911 Device summary
STR910FA STR911FA
Table 3.
Features
STR912 Device summary
STR912FA W34X6 W42X6 256+32 W44X6 512+32 96 Ethernet, USB, CAN, EMI, 80 I/Os LQFP128 LFBGA144 Z42H6 256+32 Z44H6 512+32
Flash Kbytes RAM Kbytes Peripheral functions Packages
512+32 64
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Functional overview
STR91xFAx32 STR91XFAX42 STR91xFAx44
3
3.1
Functional overview
System-in-a-Package (SiP)
The STR91xFA is a SiP device, comprised of two stacked die. One die is the ARM966E-S CPU with peripheral interfaces and analog functions, and the other die is the burst Flash. The two die are connected to each other by a custom high-speed 32-bit burst memory interface and a serial JTAG test/programming interface.
3.2
Package choice
STR91xFA devices are available in 128-pin (14 x 14 mm) 80-pin (12 x 12 mm) LQFP and LFBGA144 (10 x 10 mm) packages. Refer to Table 2 and Table 3 on page 11 for a list of available peripherals for each of the package choices.
3.3
ARM966E-S CPU core
The ARM966E-S core inherently has separate instruction and data memory interfaces (Harvard architecture), allowing the CPU to simultaneously fetch an instruction, and read or write a data item through two Tightly-Coupled Memory (TCM) interfaces as shown in Figure 1. The result is streamlined CPU Load and Store operations and a significant reduction in cycle count per instruction. In addition to this, a 5-stage pipeline is used to increase the amount of operational parallelism, giving the most performance out of each clock cycle. Ten DSP-enhanced instruction extensions are supported by this core, including single-cycle execution of 32x16 Multiply-Accumulate, saturating addition/subtraction, and count leadingzeros. The ARM966E-S core is binary compatible with 32-bit ARM7 code and 16-bit Thumb(R) code.
3.4
Burst Flash memory interface
A Burst Flash memory interface (Figure 1) has been integrated into the Instruction TCM (I-TCM) path of the ARM966E-S core. Also in this path is an 8-instruction Pre-Fetch Queue (PFQ) and a 15-entry Branch Cache (BC), enabling the ARM966E-S core to perform up to 96 MIPS while executing code directly from Flash memory. This architecture provides high performance levels without a costly instruction SRAM, instruction cache, or external SDRAM. Eliminating the instruction cache also means interrupt latency is reduced and code execution becomes more deterministic.
3.4.1
Pre-Fetch Queue (PFQ)
As the CPU core accesses sequential instructions through the I-TCM, the PFQ always looks ahead and will pre-fetch instructions, taking advantage any idle bus cycles due to variable length instructions. The PFQ will fetch 32-bits at a time from the Burst Flash memory at a rate of up to 96 MHz.
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Functional overview
3.4.2
Branch Cache (BC)
When instruction addresses are not sequential, such as a program branch situation, the PFQ would have to flush and reload which would cause the CPU to stall if no BC were present. Before reloading, the PFQ checks the BC to see if it contains the desired target branch address. The BC contains up to fifteen of the most recently taken branch addresses and the first eight instructions associated with each of these branches. This check is extremely fast, checking all fifteen BC entries simultaneously for a branch address match (cache hit). If there is a hit, the BC rapidly supplies the instruction and reduces the CPU stall. This gives the PFQ time to start pre-fetching again while the CPU consumes these eight instructions from the BC. The advantage here is that program loops (very common with embedded control applications) run very fast if the address of the loops are contained in the BC. In addition, there is a 16th branch cache entry that is dedicated to the Vectored Interrupt Controller (VIC) to further reduce interrupt latency by eliminating the stall latency typically imposed by fetching the instruction that reads the interrupt vector address from the VIC.
3.4.3
Management of literals
Typical ARM architecture and compilers do not place literals (data constants) sequentially in Flash memory with the instructions that use them, but instead the literals are placed at some other address which looks like a program branch from the PFQ's point of view. The STR91xFA implementation of the ARM966E-S core has special circuitry to prevent flushing the PFQ when literals are encountered in program flow to keep performance at a maximum.
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Functional overview Figure 1. STR91xFA block diagram STR91xA STR91x
1.8V GND 3.0 or 3.3V CORE SUPPLY, VDD
STR91xFAx32 STR91XFAX42 STR91xFAx44
Stacked Burst Flash Memory Die
JTAG ISP
Main Flash 256K or 512K Bytes
CORE GND, VSS
I/O SUPPLY, VDDQ
2nd Flash 32K Bytes
Burst Interface
GND
I/O GND, VSSQ BACKUP SUPPLY
64K or 96K Byte SRAM Arbiter
Burst Interface
VBATT
RTC
Pre-Fetch Que and Branch Cache
Data TCM Interface
Instruction ARM966E-S TCM RISC CPU Core Interface
JTAG
Control Logic / BIU and Write Buffer AMBA / AHBA Interface
JTAG Debug and ETM
ETM
32.768 kHz XTAL
Real Time Clock
Programmable Vectored Programmable Vectored Interrupt Controllers Interrupt Controller
AHB APB
Wake Up
(4) 16-bit Timers, CAPCOM, PWM
(3) UART w/ IrDA
(2) I2C
EMI Ctrl
EMI bus*** or 16 GPIO
16
External Memory Interface (EMI)***, Muxed Address/Data Programmable DMA Controller (8 ch.) USB* Full Speed, 10 Endpoints with FIFOs
32
Request from UART, I2C, SPI, Timers, Ext Req
ADC
(80) GPIO****
(2) SPI CAN 2.0B
8 Channel 10-bit ADC
48
USB Bus
Ethernet** or 16 GPIO
MUX to 48 GPIO AVDD AVREF* AVSS
4 MHz to 25 MHz XTAL
PLL, Power Management, and Supervisory Reset
AHB to APB
Motor Control, 3-ph Induction
To Ethernet PHY (MII) **
Ethernet** MAC, 10/100
Dedicated DMA
Watchdog Tmr
* USB not available on STR910
** Ethernet MAC not available on STR910 and STR911 *** EMI not available on LQFP80 **** Only 40 GPIOs on LQFP80
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Functional overview
3.5
SRAM (64K or 96K Bytes)
A 32-bit wide SRAM resides on the CPU's Data TCM (D-TCM) interface, providing singlecycle data accesses. As shown in Figure 1, the D-TCM shares SRAM access with the Advanced High-performance Bus (AHB). Sharing is controlled by simple arbitration logic to allow the DMA unit on the AHB to also access to the SRAM.
3.5.1
Arbitration
Zero-wait state access occurs for either the D-TCM or the AHB when only one of the two is requesting SRAM. When both request SRAM simultaneously, access is granted on an interleaved basis so neither requestor is starved, granting one 32-bit word transfer to each requestor before relinquishing SRAM to the other. When neither the D-TCM or the AHB are requesting SRAM, the arbiter leaves access granted to the most recent user (if D-TCM was last to use SRAM then the D-TCM will not have to arbitrate to get access next time). The CPU may execute code from SRAM through the AHB. There are no wait states as long as the D-TCM is not contending for SRAM access and the AHB is not sharing bandwidth with peripheral traffic. The ARM966E-S CPU core has a small pre-fetch queue built into this instruction path through the AHB to look ahead and fetch instructions during idle bus cycles.
3.5.2
Battery backup
When a battery is connected to the designated battery backup pin (VBATT), SRAM contents are automatically preserved when the operating voltage on the main digital supplies (VDD and VDDQ are lost or sag below the LVD threshold. Automatic switchover to SRAM can be disabled by firmware if it is desired that the battery will power only the RTC and not the SRAM during standby.
3.6
DMA data movement
DMA channels on the Advanced High-performance Bus (AHB) take full advantage of the separate data path provided by the Harvard architecture, moving data rapidly and largely independent of the instruction path. There are two DMA units, one is dedicated to move data between the Ethernet interface and SRAM, the other DMA unit has eight programmable channels with 16 request signals to service other peripherals and interfaces (USB, SSP, I2C, ADC, UART, Timers, EMI, and external request pins). Both single word and burst DMA transfers are supported. Memory-to-memory transfers are supported in addition to memoryperipheral transfers. DMA access to SRAM is shared with D-TCM accesses, and arbitration is described in Section 3.5.1. Efficient DMA transfers are managed by firmware using linked list descriptor tables. Of the 16 DMA request signals, two are assigned to external inputs. The DMA unit can move data between external devices and resources inside the STR91xFA through the EMI bus.
3.7
Non-volatile memories
There are two independent 32-bit wide Burst Flash memories enabling true read-while-write operation. The Flash memories are single-voltage erase/program with 20 year minimum data retention and 100K minimum erase cycles. The primary Flash memory is much larger than the secondary Flash.
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Functional overview
STR91xFAx32 STR91XFAX42 STR91xFAx44
Both Flash memories are blank when devices are shipped from ST. The CPU can boot only from Flash memory (configurable selection of which Flash bank). Flash memories are programmed half-word (16 bits) at a time, but are erased by sector or by full array.
3.7.1
Primary Flash memory
Using the STR91xFA device configuration software tool and 3rd party Integrated Developer Environments, it is possible to specify that the primary Flash memory is the default memory from which the CPU boots at reset, or otherwise specify that the secondary Flash memory is the default boot memory. This choice of boot memory is non-volatile and stored in a location that can be programmed and changed only by JTAG In-System Programming. See Section 6: Memory mapping, for more detail. The primary Flash memory has equal length 64K byte sectors. See Table 4 for number of sectors per device type. Table 4. Sectoring of primary Flash memory
Size of Primary Flash Number of sectors Size of each sector 256 KBytes 4 64 Kbytes 512 KBytes 8
3.7.2
Secondary Flash memory
The smaller of the two Flash memories can be used to implement a bootloader, capable of storing code to perform robust In-Application Programming (IAP) of the primary Flash memory. The CPU executes code from the secondary Flash, while updating code in the primary Flash memory. New code for the primary Flash memory can be downloaded over any of the interfaces on the STR91xFA (USB, Ethernet, CAN, UART, etc.) Additionally, the Secondary Flash memory may also be used to store small data sets by emulating EEPROM through firmware, eliminating the need for external EEPROM memories. This raises the data security level because passcodes and other sensitive information can be securely locked inside the STR91xFA device. The secondary Flash memory is sectored as shown in Table 5 according to device type. Both the primary Flash memory and the secondary Flash memory can be programmed with code and/or data using the JTAG In-System Programming (ISP) channel, totally independent of the CPU. This is excellent for iterative code development and for manufacturing. Table 5. Sectoring of secondary Flash memory
Size of Secondary Flash Number of sectors Size of each sector 32 KBytes 4 8 Kbytes
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Functional overview
3.8
One-time-programmable (OTP) memory
There are 32 bytes of OTP memory ideally suited for serial numbers, security keys, factory calibration constants, or other permanent data constants. These OTP data bytes can be programmed only one time through either the JTAG interface or by the CPU, and these bytes can never be altered afterwards. As an option, a "lock bit" can be set by the JTAG interface or the CPU which will block any further writing to the this OTP area. The "lock bit" itself is also OTP. If the OTP array is unlocked, it is always possible to go back and write to an OTP byte location that has not been previously written, but it is never possible to change an OTP byte location if any one bit of that particular byte has been written before. The last two OTP bytes (bytes 31 and 30) are reserved for the STR91xFA product ID and revision level.
3.8.1
Product ID and revision level
OTP bytes 31 and 30 are programmed at ST factory before shipment and may be read by firmware to determine the STR91xFA product type and silicon revision so it can optionally take action based on the silicon on which it is running. In Rev H devices, byte 31 contains the the major family identifier of "9" (for STR9) in the high-nibble location and the minor family identifier in the low nibble location, which can be used to determine the size of Primary flash memory. In all devices, byte 30 contains the silicon revision level indicator. See Table 6 for values related to the revisions of STR9 production devices and size of Primary Flash memory. See Section 8 for details of external identification of silicon revisions.
Table 6.
Product ID and revision level values
Silicon revision Rev D Rev G Rev H Rev H Size of Primary Flash 256K or 512K 256K or 512K 256K 512K OTP byte 31 91h 91h 90h 91h OTP byte 30 03h 20h 21h 21h
Production salestype STR91xFxxxxx STR91xFAxxxxx STR91xFAxxxxx STR91xFAxxxxx
3.9
Vectored interrupt controller (VIC)
Interrupt management in the STR91xFA is implemented from daisy-chaining two standard ARM VIC units. This combined VIC has 32 prioritized interrupt request channels and generates two interrupt output signals to the CPU. The output signals are FIQ and IRQ, with FIQ having higher priority.
3.9.1
FIQ handling
FIQ (Fast Interrupt reQuest) is the only non-vectored interrupt and the CPU can execute an Interrupt Service Routine (ISR) directly without having to determine/prioritize the interrupt source, minimizing ISR latency. Typically only one interrupt source is assigned to FIQ. An FIQ interrupt has its own set of banked registers to minimize the time to make a context switch. Any of the 32 interrupt request input signals coming into the VIC can be assigned to FIQ.
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Functional overview
STR91xFAx32 STR91XFAX42 STR91xFAx44
3.9.2
IRQ handling
IRQ is a vectored interrupt and is the logical OR of all 32 interrupt request signals coming into the 32 IRQ channels. Priority of individual vectored interrupt requests is determined by hardware (IRQ channel Intr 0 is highest priority, IRQ channel Intr 31 is lowest). However, inside the same VIC (primary or secondary VIC), CPU firmware may re-assign individual interrupt sources to individual hardware IRQ channels, meaning that firmware can effectively change interrupt priority levels as needed within the same VIC (from priority 0 to priority 16).
Note:
VIC0 (primary VIC) interrupts always have higher priority than VIC1 (secondary VIC) interrupts When the IRQ signal is activated by an interrupt request, VIC hardware will resolve the IRQ interrupt priority, then the ISR reads the VIC to determine both the interrupt source and the vector address to jump to the service code. The STR91xFA has a feature to reduce ISR response time for IRQ interrupts. Typically, it requires two memory accesses to read the interrupt vector address from the VIC, but the STR91xFA reduces this to a single access by adding a 16th entry in the instruction branch cache, dedicated for interrupts. This 16th cache entry always holds the instruction that reads the interrupt vector address from the VIC, eliminating one of the memory accesses typically required in traditional ARM implementations.
3.9.3
Interrupt sources
The 32 interrupt request signals coming into the VIC on 32 IRQ channels are from various sources; 5 from a wake-up unit and the remaining 27 come from internal sources on the STR91xFA such as on-chip peripherals, see Table 7. Optionally, firmware may force an interrupt on any IRQ channel. One of the 5 interrupt requests generated by the wake-up unit (IRQ25 in Table 7) is derived from the logical OR of all 32 inputs to the wake-up unit. Any of these 32 inputs may be used to wake up the CPU and cause an interrupt. These 32 inputs consist of 30 external interrupts on selected and enabled GPIO pins, plus the RTC interrupt, and the USB Resume interrupt. Each of 4 remaining interrupt requests generated by the wake-up unit (IRQ26 in Table 7) are derived from groupings of 8 interrupt sources. One group is from GPIO pins P3.2 to P3.7 plus the RTC interrupt and the USB Resume interrupt; the next group is from pins P5.0 to P5.7; the next group is from pins P6.0 to P6.7; and last the group is from pins P7.0 to P7.7. This allows individual pins to be assigned directly to vectored IRQ interrupts or one pin assigned directly to the non-vectored FIQ interrupt.
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STR91xFAx32 STR91XFAX42 STR91xFAx44 Table 7. VIC IRQ Channels
VIC input channel VIC0.0 VIC0.1 VIC0.2 VIC0.3 VIC0.4 VIC0.5 VIC0.6 VIC0.7 VIC0.8 VIC0.9 VIC0.10 VIC0.11 VIC0.12 VIC0.13 VIC0.14 VIC0.15 VIC1.0 VIC1.1 VIC1.2 VIC1.3 VIC1.4 VIC1.5 VIC1.6 VIC1.7 VIC1.8 VIC1.9 VIC1.10 VIC1.11 VIC1.12 Logic Block Watchdog CPU Firmware CPU Core CPU Core TIM Timer 0 TIM Timer 1 TIM Timer 2 TIM Timer 3 USB USB CCU Ethernet MAC DMA CAN IMC ADC UART0 UART1 UART2 I2C0 I2C1 SSP0 SSP1 BROWNOUT RTC Wake-Up (all) Wake-up Group 0 Wake-up Group 1 Wake-up Group 2
Functional overview
IRQ Channel hardware priority 0 (high priority) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Interrupt Source Timeout in WDT mode, Terminal Count in Counter Mode Firmware generated interrupt Debug Receive Command Debug Transmit Command Logic OR of ICI0_0, ICI0_1, OCI0_0, OCI0_1, Timer overflow Logic OR of ICI1_0, ICI1_1, OCI1_0, OCI1_1, Timer overflow Logic OR of ICI2_0, ICI2_1, OCI2_0, OCI2_1, Timer overflow Logic OR of ICI3_0, ICI3_1, OCI3_0, OCI3_1, Timer overflow Logic OR of high priority USB interrupts Logic OR of low priority USB interrupts Logic OR of all interrupts from Clock Control Unit Logic OR of Ethernet MAC interrupts via its own dedicated DMA channel. Logic OR of interrupts from each of the 8 individual DMA channels Logic OR of all CAN interface interrupt sources Logic OR of 8 Induction Motor Control Unit interrupts End of AtoD conversion interrupt Logic OR of 5 interrupts from UART channel 0 Logic OR of 5 interrupts from UART channel 1 Logic OR of 5 interrupts from UART channel 2 Logic OR of transmit, receive, and error interrupts of I2C channel 0 Logic OR of transmit, receive, and error interrupts of I2C channel 1 Logic OR of all interrupts from SSP channel 0 Logic OR of all interrupts from SSP channel 1 LVD warning interrupt Logic OR of Alarm, Tamper, or Periodic Timer interrupts Logic OR of all 32 inputs of Wake-Up unit (30 pins, RTC, and USB Resume) Logic OR of 8 interrupt sources: RTC, USB Resume, pins P3.2 to P3.7 Logic OR of 8 interrupts from pins P5.0 to P5.7 Logic OR of 8 interrupts from pins P6.0 to P6.7
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Functional overview Table 7. VIC IRQ Channels (continued)
VIC input channel VIC1.13 VIC1.14 VIC1.15 Logic Block Wake-up Group 3 USB PFQ-BC
STR91xFAx32 STR91XFAX42 STR91xFAx44
IRQ Channel hardware priority 29 30 31 (low priority)
Interrupt Source Logic OR of 8 interrupts from pins P7.0 to P7.7 USB Bus Resume Wake-up (also input to wake-up unit) Special use of interrupts from Prefetch Queue and Branch Cache
3.10
Clock control unit (CCU)
The CCU generates a master clock of frequency fMSTR. From this master clock the CCU also generates individually scaled and gated clock sources to each of the following functional blocks within the STR91xFA.

CPU, fCPUCLK Advanced High-performance Bus (AHB), fHCLK Advanced Peripheral Bus (APB), fPCLK Flash Memory Interface (FMI), fFMICLK External Memory Interface (EMI), fBCLK UART Baud Rate Generators, fBAUD USB, fUSB
3.10.1
Master clock sources
The master clock in the CCU (fMSTR) is derived from one of three clock input sources. Under firmware control, the CPU can switch between the three CCU inputs without introducing any glitches on the master clock output. Inputs to the CCU are:
Main Oscillator (fOSC). The source for the main oscillator input is a 4 to 25 MHz external crystal connected to STR91xFA pins X1_CPU and X2_CPU, or an external oscillator device connected to pin X1_CPU. PLL (fPLL). The PLL takes the 4 to 25 MHz oscillator clock as input and generates a master clock output up to 96 MHz (programmable). By default, at power-up the master clock is sourced from the main oscillator until the PLL is ready (locked) and then the CPU may switch to the PLL source under firmware control. The CPU can switch back to the main oscillator source at any time and turn off the PLL for low-power operation. The PLL is always turned off in Sleep mode. RTC (fRTC). A 32.768 kHz external crystal can be connected to pins X1_RTC and X2_RTC, or an external oscillator connected to pin X1_RTC to constantly run the realtime clock unit. This 32.768 kHz clock source can also be used as an input to the CCU to run the CPU in slow clock mode for reduced power.
As an option, there are a number of peripherals that do not have to receive a clock sourced from the CCU. The USB interface can receive an external clock on pin P2.7, TIM timers TIM0/ TIM1 can receive an external clock on pin P2.4, and timers TIM2/TIM3 on pin P2.5.
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STR91xFAx32 STR91XFAX42 STR91xFAx44 Figure 2. Clock control
32.768 kHz
JRTCLK 25MHz RTCSEL
Functional overview
EMI_BCLK PHYSEL RCLK 1/2 HCLK
MII_PHYCLK
X1_CPU 4-25MHz X1_CPU
AHB DIV
(1,2,4) PCLK
Main OSC
PLL
fOSC
fPLL
fMSTR
RCLK DIV
(1,2,4,8,16,1024)
APB DIV)
(1,2,4,8)
X1_RTC X2_RTC
RTC OSC
32.768 kHz fRTC
Master CLK
FMICLK 1/2
EXTCLK_T0T1
Timer 0 & 1 External clock
CPUCLK
BRCLK EXTCLK_T2T3 Timer 2 & 3 External clock 1/2 To UART
USBCLK USB_CLK48M 48MHz 1/2 To USB
3.10.2
Reference clock (RCLK)
The main clock (fMSTR) can be divided to operate at a slower frequency reference clock (RCLK) for the ARM core and all the peripherals. The RCLK provides the divided clock for the ARM core, and feeds the dividers for the AHB, APB, External Memory Interface, and FMI units.
3.10.3
AHB clock (HCLK)
The RCLK can be divided by 1, 2 or 4 to generate the AHB clock. The AHB clock is the bus clock for the AHB bus and all bus transfers are synchronized to this clock. The maximum HCLK frequency is 96 MHz.
3.10.4
APB clock (PCLK)
The RCLK can be divided by 1, 2, 4 or 8 to generate the APB clock. The APB clock is the bus clock for the APB bus and all bus transfers are synchronized to this clock. Many of the peripherals that are connected to the AHB bus also use the PCLK as the source for external bus data transfers. The maximum PCLK frequency is 48 MHz.
3.10.5
Flash memory interface clock (FMICLK)
The FMICLK clock is an internal clock derived from RCLK, defaulting to RCLK frequency at power up. The clock can be optionally divided by 2. The FMICLK determines the bus bandwidth between the ARM core and the Flash memory. Typically, codes in the Flash memory can be fetched one word per FMICLK clock in burst mode. The maximum FMICLK frequency is 96MHz.
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Functional overview
STR91xFAx32 STR91XFAX42 STR91xFAx44
3.10.6
Baud rate clock (BRCLK)
The baud rate clock is an internal clock derived from fMSTR that is used by the three on-chip UART peripherals for baudrate generation. The frequency can be optionally divided by 2.
3.10.7
External memory interface bus clock (BCLK)
The BCLK is an internal clock that controls the EMI bus. All EMI bus signals are synchronized to the BCLK. The BCLK is derived from the HCLK and the frequency can be configured to be the same or half that of the HCLK. Refer to Table 17 on page 64 for the maximum BCLK frequency (fBCLK). The BCLK clock is available on the LFBGA package as an output pin.
3.10.8
USB interface clock
Special consideration regarding the USB interface: The clock to the USB interface must operate at 48 MHz and comes from one of three sources, selected under firmware control:

CCU master clock output of 48 MHz. CCU master clock output of 96 MHz. An optional divided-by-two circuit is available to produce 48 MHz for the USB while the CPU system runs at 96MHz. STR91xFA pin P2.7. An external 48 MHz oscillator connected to pin P2.7 can directly source the USB while the CCU master clock can run at some frequency other than 48 or 96 MHz.
3.10.9
Ethernet MAC clock
Special consideration regarding the Ethernet MAC: The external Ethernet PHY interface device requires it's own 25 MHz clock source. This clock can come from one of two sources:
A 25 MHz clock signal coming from a dedicated output pin (P5.2) of the STR91xFA. In this case, the STR91xFA must use a 25 MHz signal on its main oscillator input in order to pass this 25 MHz clock back out to the PHY device through pin P5.2. The advantage here is that an inexpensive 25 MHz crystal may be used to source a clock to both the STR91xFA and the external PHY device. An external 25 MHz oscillator connected directly to the external PHY interface device. In this case, the STR91xFA can operate independent of 25 MHz.
3.10.10
External RTC calibration clock
The RTC_CLK can be enabled as an output on the JRTCK pin. The RTC_CLK is used for RTC oscillator calibration. The RTC_CLK is active in Sleep mode and can be used as a system wake up control clock.
3.10.11
Operation example
As an example of CCU operation, a 25 MHz crystal can be connected to the main oscillator input on pins X1_CPU and X2_CPU, a 32.768 kHz crystal connected to pins X1_RTC and X2_RTC, and the clock input of an external Ethernet PHY device is connected to STR91xFA output pin P5.2. In this case, the CCU can run the CPU at 96 MHz from PLL, the USB interface at 48 MHz, and the Ethernet interface at 25 MHz. The RTC is always running in the background at 32.768 kHz, and the CPU can go to very low power mode dynamically by running from 32.768 kHz and shutting off peripheral clocks and the PLL as needed.
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Functional overview
3.11
Flexible power management
The STR91xFA offers configurable and flexible power management control that allows the user to choose the best power option to fit the application. Power consumption can be dynamically managed by firmware and hardware to match the system's requirements. Power management is provided via clock control to the CPU and individual peripherals. Clocks to the CPU and peripherals can be individually divided and gated off as needed. In addition to individual clock divisors, the CCU master clock source going to the CPU, AHB, APB, EMI, and FMI can be divided dynamically by as much as 1024 for low power operation. Additionally, the CCU may switch its input to the 32.768 kHz RTC clock at any time for low power. The STR91xFA supports the following three global power control modes:

Run Mode: All clocks are on with option to gate individual clocks off via clock mask registers. Idle Mode: CPU and FMI clocks are off until an interrupt, reset, or wake-up occurs. Pre-configured clock mask registers selectively allow individual peripheral clocks to continue run during Idle Mode. Sleep Mode: All clocks off except RTC clock. Wake up unit remains powered, PLL is forced off.
A special mode is used when JTAG debug is active which never gates off any clocks even if the CPU enters Idle or Sleep mode.
3.11.1
Run mode
This is the default mode after any reset occurs. Firmware can gate off or scale any individual clock. Also available is a special Interrupt Mode which allows the CPU to automatically run full speed during an interrupt service and return back to the selected CPU clock divisor rate when the interrupt has been serviced. The advantage here is that the CPU can run at a very low frequency to conserve power until a periodic wake-up event or an asynchronous interrupt occurs at which time the CPU runs full speed immediately.
3.11.2
Idle mode
In this mode the CPU suspends code execution and the CPU and FMI clocks are turned off immediately after firmware sets the Idle Bit. Various peripherals continue to run based on the settings of the mask registers that exist just prior to entering Idle Mode. There are 3 ways to exit Idle Mode and return to Run Mode:

Any reset (external reset pin, watchdog, low-voltage, power-up, JTAG debug command) Any interrupt (external, internal peripheral, RTC alarm or interval) Input from wake-up unit on GPIO pins
Note:
It is possible to remain in Idle Mode for the majority of the time and the RTC can be programmed to periodically wake up to perform a brief task or check status.
3.11.3
Sleep mode
In this mode all clock circuits except the RTC are turned off and main oscillator input pins X1_CPU and X2_CPU are disabled. The RTC clock is required for the CPU to exit Sleep
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Functional overview
STR91xFAx32 STR91XFAX42 STR91xFAx44
Mode. The entire chip is quiescent (except for RTC and wake-up circuitry). There are three means to exit Sleep Mode and re-start the system:

Some resets (external reset pin, low-voltage, power-up, JTAG debug command) RTC alarm Input from wake-up unit
3.12
Voltage supplies
The STR91xFA requires two separate operating voltage supplies. The CPU and memories operate from a 1.65V to 2.0V on the VDD pins, and the I/O ring operates at 2.7V to 3.6V on the VDDQ pins.
3.12.1
Independent A/D converter supply and reference voltage
The ADC unit on 128-pin and 144-ball packages has an isolated analog voltage supply input at pin AVDD to accept a very clean voltage source, independent of the digital voltage supplies. Additionally, an isolated analog supply ground connection is provided on pin AVSS only on 128-pin and 144-ball packages for further ADC supply isolation. On 80-pin packages, the analog voltage supply is shared with the ADC reference voltage pin (as described next), and the analog ground is shared with the digital ground at a single point in the STR91xFA device on pin AVSS_VSSQ. A separate external analog reference voltage input for the ADC unit is available on 128-pin and 144-ball packages at the AVREF pin for better accuracy on low voltage inputs. For 80pin packages, the ADC reference voltage is tied internally to the ADC unit supply voltage at pin AVREF_AVDD, meaning the ADC reference voltage is fixed to the ADC unit supply voltage. See Table 12: Operating conditions, for restrictions to the relative voltage levels of VDDQ, AVDD, AVREF, and AVREF_AVDD.
3.12.2
Battery supply
An optional stand-by voltage from a battery or other source may be connected to pin VBATT to retain the contents of SRAM in the event of a loss of the main digital supplies (VDD and VDDQ) . The SRAM will automatically switch its supply from the internal VDD source to the VBATT pin when the voltage of VDD drops below the LVD threshold (and not VBAT). In order to use the battery supply, the LVD must be enabled. The VBATT pin also supplies power to the RTC unit, allowing the RTC to function even when the main digital supplies (VDD and VDDQ) are switched off. By configuring the RTC register, it is possible to select whether or not to power from VBATT only the RTC unit, or power the RTC unit and the SRAM when the STR91xFA device is powered off.
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Functional overview
3.13
System supervisor
The STR91xFA monitors several system and environmental inputs and will generate a global reset, a system reset, or an interrupt based on the nature of the input and configurable settings. A global reset clears all functions on the STR91xFA, a system reset will clear all but the Clock Control Unit (CCU) settings and the system status register. At any time, firmware may reset individual on-chip peripherals. System supervisor inputs include:

GR: CPU voltage supply (VDD) drop out or brown out GR: I/O voltage supply (VDDQ) drop out or brown out GR: Power-Up condition SR: Watchdog timer timeout SR: External reset pin (RESET_INn) SR: JTAG debug reset command
Note:
GR: means the input causes Global Reset, SR: means the input causes System Reset The CPU may read a status register after a reset event to determine if the reset was caused by a watchdog timer timeout or a voltage supply drop out. This status register is cleared only by a power up reset.
3.13.1
Supply voltage brownout
Each operating voltage source (VDD and VDDQ) is monitored separately by the Low Voltage Detect (LVD) circuitry. The LVD will generate an early warning interrupt to the CPU when voltage sags on either VDD or VDDQ voltage inputs. This is an advantage for battery powered applications because the system can perform an orderly shutdown before the batteries become too weak. The voltage trip point to cause a brown out interrupt is typically 0.25V above the LVD dropout thresholds that cause a reset. CPU firmware may prevent all brown-out interrupts by writing to interrupt mask registers at run-time.
3.13.2
Supply voltage dropout
LVD circuitry will always cause a global reset if the CPU's VDD source drops below it's fixed threshold of 1.4V. However, the LVD trigger threshold to cause a global reset for the I/O ring's VDDQ source is set to one of two different levels, depending if VDDQ will be operated in the range of 2.7V to 3.3V, or 3.0V to 3.6V. If VDDQ operation is at 2.7V to 3.3V, the LVD dropout trigger threshold is 2.4V. If VDDQ operation is 3.0V and 3.6V, the LVD threshold is 2.7V. The choice of trigger level is made by STR91xFA device configuration software from STMicroelectronics or IDE from 3rd parties, and is programmed into the STR91xFA device along with other configurable items through the JTAG interface when the Flash memory is programmed. CPU firmware may prevent some LVD resets if desired by writing a control register at runtime. Firmware may also disable the LVD completely for lowest-power operation when an external LVD device is being used.
3.13.3
Watchdog timer
The STR91xFA has a 16-bit down-counter (not one of the four TIM timers) that can be used as a watchdog timer or as a general purpose free-running timer/counter. The clock source is the peripheral clock from the APB, and an 8-bit clock pre-scaler is available. When enabled
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Functional overview
STR91xFAx32 STR91XFAX42 STR91xFAx44
by firmware as a watchdog, this timer will cause a system reset if firmware fails to periodically reload this timer before the terminal count of 0x0000 occurs, ensuring firmware sanity. The watchdog function is off by default after a reset and must be enabled by firmware.
3.13.4
External RESET_INn pin
This input signal is active-low with hystereses (VRHYS). Other open-drain, active-low system reset signals on the circuit board (such as closure to ground from a push-button) may be connected directly to the RESET_INn pin, but an external pull-up resistor to VDDQ must be present as there is no internal pullup on the RESET_INn pin. A valid active-low input signal of tRINMIN duration on the RESET_INn pin will cause a system reset within the STR91xFA. There is also a RESET_OUTn pin on the STR91xFA that can drive other system components on the circuit board. RESET_OUTn is active-low and has the same timing of the Power-On-Reset (POR) shown next, tPOR.
3.13.5
Power-up
The LVD circuitry will always generate a global reset when the STR91xFA powers up, meaning internal reset is active until VDDQ and VDD are both above the LVD thresholds. This POR condition has a duration of tPOR, after which the CPU will fetch its first instruction from address 0x0000.0000 in Flash memory. It is not possible for the CPU to boot from any other source other than Flash memory.
3.13.6
JTAG debug command
When the STR91xFA is in JTAG debug mode, an external device which controls the JTAG interface can command a system reset to the STR91xFA over the JTAG channel.
3.13.7
Tamper detection
On 128-pin and 144-ball STR91xFA devices only, there is a tamper detect input pin, TAMPER_IN, used to detect and record the time of a tamper event on the end product such as malicious opening of an enclosure, unwanted opening of a panel, etc. The activation mode of the tamper pin is programmable to one of two modes. One is Normally Closed/Tamper Open, the other mode will detect when a signal on the tamper input pin is driven from low-to-high, or high-to-low depending on firmware configuration. Once a tamper event occurs, the RTC time (millisecond resolution) and the date are recorded in the RTC unit. Simultaneously, the SRAM standby voltage source will be cut off to invalidate all SRAM contents. Tamper detection control and status logic are part of the RTC unit.
3.14
Real-time clock (RTC)
The RTC combines the functions of a complete time-of-day clock (millisecond resolution) with an alarm programmable up to one month, a 9999-year calender with leap-year support, periodic interrupt generation from 1 to 512 Hz, tamper detection (described in Section 3.13.7), and an optional clock calibration output on the JRTCK pin. The time is in 24 hour mode, and time/calendar values are stored in binary-coded decimal format. The RTC also provides a self-isolation mode that is automatically activated during power down. This feature allows the RTC to continue operation when VDDQ and VDD are absent, as long as an alternate power source, such as a battery, is connected to the VBATT input
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Functional overview
pin. The current drawn by the RTC unit on the VBATT pin is very low in this standby mode, IRTC_STBY.
3.15
JTAG interface
An IEEE-1149.1 JTAG interface on the STR91xFA provides In-System-Programming (ISP) of all memory, boundary scan testing of pins, and the capability to debug the CPU. STR91xFA devices are shipped from ST with blank Flash memories. The CPU can only boot from Flash memory (selection of which Flash bank is programmable). Firmware must be initially programmed through JTAG into one of these Flash memories before the STR91xFA is used. Six pins are used on this JTAG serial interface. The five signals JTDI, JTDO, JTMS, JTCK, and JTRSTn are all standard JTAG signals complying with the IEEE-1149.1 specification. The sixth signal, JRTCK (Return TCK), is an output from the STR91xFA and it is used to pace the JTCK clock signal coming in from the external JTAG test equipment for debugging. The frequency of the JTCK clock signal coming from the JTAG test equipment must be at least 10 times less than the ARM966E-S CPU core operating frequency (fCPUCLK). To ensure this, the signal JRTCK is output from the STR91xFA and is input to the external JTAG test equipment to hold off transitions of JTCK until the CPU core is ready, meaning that the JTAG equipment cannot send the next rising edge of JTCK until the equipment receives a rising edge of JRTCK from the STR91xFA. The JTAG test equipment must be able to interpret the signal JRTCK and perform this adaptive clocking function. If it is known that the CPU clock will always be at least ten times faster than the incoming JTCK clock signal, then the JRTCK signal is not needed. The two die inside the STR91xFA (CPU die and Flash memory die) are internally daisychained on the JTAG bus, see Figure 3 on page 28. The CPU die has two JTAG Test Access Ports (TAPs), one for boundary scan functions and one for ARM CPU debug. The Flash memory die has one TAP for program/erase of non-volatile memory. Because these three TAPs are daisy-chained, only one TAP will converse on the JTAG bus at any given time while the other two TAPs are in BYPASS mode. The TAP positioning order within this JTAG chain is the boundary scan TAP first, followed by the ARM debug TAP, followed by the Flash TAP. All three TAP controllers are reset simultaneously by one of two methods:

A chip-level global reset, caused only by a Power-On-Reset (POR) or a Low Voltage Detect (LVD). A reset command issued by the external JTAG test equipment. This can be the assertion of the JTAG JTRSTn input pin on the STR91xFA or a JTAG reset command shifted into the STR91xFA serially.
This means that chip-level system resets from watchdog time-out or the assertion of RESET_INn pin do not affect the operation of any JTAG TAP controller. Only global resets effect the TAPs.
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Functional overview Figure 3.
STR91xFAx32 STR91XFAX42 STR91xFAx44 JTAG chaining inside the STR91xFA
STR91xx
MAIN FLASH SECONDARY FLASH BURST FLASH MEMORY DIE
JTAG TAP CONTROLLER #3 TDO TMS TCK TRST TDI
JTAG Instruction register length is 8 bits
JTDO JTRSTn JTCK JTMS JTDI ARM966ES DIE
JRTCK
TDI
TMS
TCK TRST
TDO
TDI
TRST
TCK
TMS
TDO
JTAG TAP CONTROLLER #1
JTAG TAP CONTROLLER #2
JTAG Instruction register length: 5 bits for TAP #1 4 bits for TAP #2
BOUNDARY SCAN
CPU DEBUG
3.15.1
In-system-programming
The JTAG interface is used to program or erase all memory areas of the STR91xFA device. The pin RESET_INn must be asserted during ISP to prevent the CPU from fetching invalid instructions while the Flash memories are being programmed. Note that the 32 bytes of OTP memory locations cannot be erased by any means once programmed by JTAG ISP or the CPU.
3.15.2
Boundary scan
Standard JTAG boundary scan testing compliant with IEEE-1149.1 is available on the majority of pins of the STR91xFA for circuit board test during manufacture of the end product. STR91xFA pins that are not serviced by boundary scan are the following:

JTAG pins JTCK, JTMS, JTDI, JTDO, JTRSTn, JRTCK Oscillator input pins X1_CPU, X2_CPU, X1_RTC, X2_RTC Tamper detect input pin TAMPER_IN (128-pin and 144-pin packages only)
3.15.3
CPU debug
The ARM966E-S CPU core has standard ARM EmbeddedICE-RT logic, allowing the STR91xFA to be debugged through the JTAG interface. This provides advanced debugging features making it easier to develop application firmware, operating systems, and the hardware itself. Debugging requires that an external host computer, running debug software, is connected to the STR91xFA target system via hardware which converts the stream of debug data and commands from the host system's protocol (USB, Ethernet, etc.) to the
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Functional overview
JTAG EmbeddedICE-RT protocol on the STR91xFA. These protocol converters are commercially available and operate with debugging software tools. The CPU may be forced into a Debug State by a breakpoint (code fetch), a watchpoint (data access), or an external debug request over the JTAG channel, at which time the CPU core and memory system are effectively stopped and isolated from the rest of the system. This is known as Halt Mode and allows the internal state of the CPU core, memory, and peripherals to be examined and manipulated. Typical debug functions are supported such as run, halt, and single-step. The EmbeddedICE-RT logic supports two hardware compare units. Each can be configured to be either a watchpoint or a breakpoint. Breakpoints can also be datadependent. Debugging (with some limitations) may also occur through the JTAG interface while the CPU is running full speed, known as Monitor Mode. In this case, a breakpoint or watchpoint will not force a Debug State and halt the CPU, but instead will cause an exception which can be tracked by the external host computer running monitor software. Data can be sent and received over the JTAG channel without affecting normal instruction execution. Time critical code, such as Interrupt Service Routines may be debugged real-time using Monitor Mode.
3.15.4
JTAG security bit
This is a non-volatile bit (Flash memory based), which when set will not allow the JTAG debugger or JTAG programmer to read the Flash memory contents. Using JTAG ISP, this bit is typically programmed during manufacture of the end product to prevent unwanted future access to firmware intellectual property. The JTAG Security Bit can be cleared only by a JTAG "Full Chip Erase" command, making the STR91xFA device blank (except for programmed OTP bytes), and ready for programming again. The CPU can read the status of the JTAG Security Bit, but it may not change the bit value.
3.16
Embedded trace module (ARM ETM9, v. r2p2)
The ETM9 interface provides greater visibility of instruction and data flow happening inside the CPU core by streaming compressed data at a very high rate from the STR91xFA though a small number of ETM9 pins to an external Trace Port Analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or other high-speed channel. Real-time instruction flow and data activity can be recorded and later formatted and displayed on the host computer running debugger software, and this software is typically integrated with the debug software used for EmbeddedICE-RT functions such as single-step, breakpoints, etc. Tracing may be triggered and filtered by many sources, such as instruction address comparators, data watchpoints, context ID comparators, and counters. State sequencing of up to three triggers is also provided. TPA hardware is commercially available and operates with debugging software tools. The ETM9 interface is nine pins total, four of which are data lines, and all pins can be used for GPIO after tracing is no longer needed. The ETM9 interface is used in conjunction with the JTAG interface for trace configuration. When tracing begins, the ETM9 engine compresses the data by various means before broadcasting data at high speed to the TPA over the four data lines. The most common ETM9 compression technique is to only output address information when the CPU branches to a location that cannot be inferred from the source code. This means the host computer must have a static image of the code being executed for decompressing the ETM9 data. Because of this, self-modified code cannot be traced.
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Functional overview
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3.17
Ethernet MAC interface with DMA
STR91xFA devices in 128-pin and 144-ball packages provide an IEEE-802.3-2002 compliant Media Access Controller (MAC) for Ethernet LAN communications through an industry standard Medium Independent Interface (MII). The STR91xFA requires an external Ethernet physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the STR91xFA MII port using as many as 18 signals (see pins which have signal names MII_* in Table 9). The MAC corresponds to the OSI Data Link layer and the PHY corresponds to the OSI Physical layer. The STR91xFA MAC is responsible for:

Data encapsulation, including frame assembly before transmission, and frame parsing/error detection during and after reception. Media access control, including initiation of frame transmission and recover from transmission failure. Supports 10 and 100 Mbps rates Tagged MAC frame support (VLAN support) Half duplex (CSMA/CD) and full duplex operation MAC control sublayer (control frames) support 32-bit CRC generation and removal Several address filtering modes for physical and multicast address (multicast and group addresses) 32-bit status code for each transmitted or received frame Internal FIFOs to buffer transmit and receive frames. Transmit FIFO depth is 4 words (32 bits each), and the receive FIFO is 16 words deep.
The STR91xFA MAC includes the following features:

A 32-bit burst DMA channel residing on the AHB is dedicated to the Ethernet MAC for highspeed data transfers, side-stepping the CPU for minimal CPU impact during transfers. This DMA channel includes the following features:

Direct SRAM to MAC transfers of transmit frames with the related status, by descriptor chain Direct MAC to SRAM transfers of receive frames with the related status, by descriptor chain Open and Closed descriptor chain management
3.18
USB 2.0 slave device interface with DMA
The STR91xFA provides a USB slave controller that implements both the OSI Physical and Data Link layers for direct bus connection by an external USB host on pins USBDP and USBPN. The USB interface detects token packets, handles data transmission and reception, and processes handshake packets as required by the USB 2.0 standard.
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STR91xFAx32 STR91XFAX42 STR91xFAx44 The USB slave interface includes the following features:

Functional overview
Supports USB low and full-speed transfers (12 Mbps), certified to comply with the USB 2.0 specification Supports isochronous, bulk, control, and interrupt endpoints Configurable number of endpoints allowing a mixture of up to 20 single-buffered monodirectional endpoints or up to 10 double-buffered bidirectional endpoints Dedicated, dual-port 2 Kbyte USB Packet Buffer SRAM. One port of the SRAM is connected by a Packet Buffer Interface (PBI) on the USB side, and the CPU connects to the other SRAM port. CRC generation and checking NRZI encoding-decoding and bit stuffing USB suspend resume operations

3.18.1
Packet buffer interface (PBI)
The PBI manages a set of buffers inside the 2 Kbyte Packet Buffer, both for transmission and reception. The PBI will choose the proper buffer according to requests coming from the USB Serial Interface Engine (SIE) and locate it in the Packet SRAM according to addresses pointed by endpoint registers. The PBI will also auto-increment the address after each exchanged byte until the end of packet, keeping track of the number of exchanged bytes and preventing buffer overrun. Special support is provided by the PBI for isochronous and bulk transfers, implementing double-buffer usage which ensures there is always an available buffer for a USB packet while the CPU uses a different buffer.
3.18.2
DMA
A programmable DMA channel may be assigned by CPU firmware to service the USB interface for fast and direct transfers between the USB bus and SRAM with little CPU involvement. This DMA channel includes the following features:

Direct USB Packet Buffer SRAM to system SRAM transfers of receive packets, by descriptor chain for bulk or isochronous endpoints. Direct system SRAM to USB Packet Buffer SRAM transfers of transmit packets, by descriptor chain for bulk or isochronous endpoints. Linked-list descriptor chain support for multiple USB packets
3.18.3
Suspend mode
CPU firmware may place the USB interface in a low-power suspend mode when required, and the USB interface will automatically wake up asynchronously upon detecting activity on the USB pins.
3.19
CAN 2.0B interface
The STR91xFA provides a CAN interface complying with CAN protocol version 2.0 parts A and B. An external CAN transceiver device connected to pins CAN_RX and CAN_TX is required for connection to the physical CAN bus. The CAN interface manages up to 32 Message Objects and Identifier Masks using a Message SRAM and a Message Handler. The Message Handler takes care of low-level CAN bus activity such as acceptance filtering, transfer of messages between the CAN bus
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Functional overview
STR91xFAx32 STR91XFAX42 STR91xFAx44
and the Message SRAM, handling of transmission requests, and interrupt generation. The CPU has access to the Message SRAM via the Message Handler using a set of 38 control registers. The follow features are supported by the CAN interface:

Bitrates up to 1 Mbps Disable Automatic Retransmission mode for Time Triggered CAN applications 32 Message Objects Each Message Object has its own Identifier Mask Programmable FIFO mode Programmable loopback mode for self-test operation
The CAN interface is not supported by DMA.
3.20
UART interfaces with DMA
The STR91xFA supports three independent UART serial interfaces, designated UART0, UART1, and UART2. Each interface is very similar to the industry-standard 16C550 UART device. All three UART channels support IrDA encoding/decoding, requiring only an external LED transceiver to pins UARTx_RX and UARTx_Tx for communication. One UART channel (UART0) supports full modem control signals. UART interfaces include the following features:

Maximum baud rate of 1.5 Mbps Separate FIFOs for transmit and receive, each 16 deep, each FIFO can be disabled by firmware if desired Programmable FIFO trigger levels between 1/8 and 7/8 Programmable baud rate generator based on CCU master clock, or CCU master clock divided by two Programmable serial data lengths of 5, 6, 7, or 8 bits with start bit and 1 or 2 stop bits Programmable selection of even, odd, or no-parity bit generation and detection False start-bit detection Line break generation and detection Support of IrDA SIR ENDEC functions for data rates of up to 115.2K bps IrDA bit duration selection of 3/16 or low-power (1.14 to 2.23 sec) Channel UART0 supports modem control functions CTS, DCD, DSR, RTS, DTR, and RI
For your reference, only two standard 16550 UART features are not supported, 1.5 stop bits and independent receive clock.
3.20.1
DMA
A programmable DMA channel may be assigned by CPU firmware to service channels UART0 and UART1 for fast and direct transfers between the UART bus and SRAM with little CPU involvement. Both DMA single-transfers and DMA burst-transfers are supported for transmit and receive. Burst transfers require that UART FIFOs are enabled.
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Functional overview
3.21
I2C interfaces with DMA
The STR91xFA supports two independent I2C serial interfaces, designated I2C0, and I2C1. Each interface allows direct connection to an I2C bus as either a bus master or bus slave device (firmware configurable). I2C is a two-wire communication channel, having a bidirectional data signal and a single-directional clock signal based on open-drain line drivers, requiring external pull-up resistors. Byte-wide data is transferred between a Master device and a Slave device on two wires. More than one bus Master is allowed, but only one Master may control the bus at any given time. Data is not lost when another Master requests the use of a busy bus because I2C supports collision detection and arbitration. More than one Slave device may be present on the bus, each having a unique address. The bus Master initiates all data movement and generates the clock that permits the transfer. Once a transfer is initiated by the Master, any device that is addressed is considered a Slave. Automatic clock synchronization allows I2C devices with different bit rates to communicate on the same physical bus. A single device can play the role of Master or Slave, or a single device can be a Slave only. A Master or Slave device has the ability to suspend data transfers if the device needs more time to transmit or receive data. Each I2C interface on the STR91xFA has the following features:

Programmable clock supports various rates up to I2C Standard rate (100 KHz) or Fast rate (400 KHz). Serial I/O Engine (SIOE) takes care of serial/parallel conversion; bus arbitration; clock generation and synchronization; and handshaking Multi-master capability 7-bit or 10-bit addressing
3.21.1
DMA
A programmable DMA channel may be assigned by CPU firmware to service each I2C channel for fast and direct transfers between the I2C bus and SRAM with little CPU involvement. Both DMA single-transfers and DMA burst-transfers are supported for transmit and receive.
3.22
SSP interfaces (SPI, SSI, and Microwire) with DMA
The STR91xFA supports two independent Synchronous Serial Port (SSP) interfaces, designated SSP0, and SSP1. Primary use of each interface is for supporting the industry standard Serial Peripheral Interface (SPI) protocol, but also supporting the similar Synchronous Serial Interface (SSI) and Microwire communication protocols. SPI is a three or four wire synchronous serial communication channel, capable of full-duplex operation. In three-wire configuration, there is a clock signal, and two data signals (one data signal from Master to Slave, the other from Slave to Master). In four-wire configuration, an additional Slave Select signal is output from Master and received by Slave. The SPI clock signal is a gated clock generated from the Master and regulates the flow of data bits. The Master may transmit at a variety of baud rates, up to 24 MHz In multi-Slave operation, no more than one Slave device can transmit data at any given time. Slave selection is accomplished when a Slave's "Slave Select" input is permanently grounded or asserted active-low by a Master device. Slave devices that are not selected do
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Functional overview
STR91xFAx32 STR91XFAX42 STR91xFAx44
not interfere with SPI activities. Slave devices ignore the clock signals and keep their data output pins in high-impedance state when not selected. The STR91xFA supports SPI multiMaster operation because it provides collision detection. Each SSP interface on the STR91xFA has the following features:

Full-duplex, three or four-wire synchronous transfers Master or Slave operation Programmable clock bit rate with prescaler, up to 24 MHz for Master mode and 4 MHz for Slave mode Separate transmit and receive FIFOs, each 16-bits wide and 8 locations deep Programmable data frame size from 4 to 16 bits Programmable clock and phase polarity Specifically for Microwire protocol: - - - Half-duplex transfers using 8-bit control message Full-duplex four-wire synchronous transfer Transmit data pin tri-stateable when not transmitting Specifically for SSI protocol:
3.22.1
DMA
A programmable DMA channel may be assigned by CPU firmware to service each SSP channel for fast and direct transfers between the SSP bus and SRAM with little CPU involvement. Both DMA single-transfers and DMA burst-transfers are supported for transmit and receive. Burst transfers require that FIFOs are enabled.
3.23
General purpose I/O
There are up to 80 GPIO pins available on 10 I/O ports for 128-pin and 144-ball devices, and up to 40 GPIO pins on 5 I/O ports for 80-pin devices. Each and every GPIO pin by default (during and just after a reset condition) is in high-impedance input mode, and some GPIO pins are additionally routed to certain peripheral function inputs. CPU firmware may initialize GPIO pins to have alternate input or output functions as listed in Table 9. At any time, the logic state of any GPIO pin may be read by firmware as a GPIO input, regardless of its reassigned input or output function. Bit masking is available on each port, meaning firmware may selectively read or write individual port pins, without disturbing other pins on the same port during a write. Firmware may designate each GPIO pin to have open-drain or push-pull characteristics. All GPIO pins are 5V tolerant, meaning in they can drive a voltage level up to VDDQ, and can be safely driven by a voltage up to 5.5V. There are no internal pull-up or pull-down resistors on GPIO pins. As such, it is recommended to ground, or pull up to VDDQ with a 100K resistor, all unused GPIO pins to minimize power consumption and noise generation.
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Functional overview
3.24
A/D converter (ADC) with DMA
The STR91xFA provides an eight-channel, 10-bit successive approximation analog-todigital converter. The ADC input pins are multiplexed with other functions on Port 4 as shown in Table 9. Following are the major ADC features:

Fast conversion time, as low as 0.7 usec Accuracy. Integral and differential non-linearity are typically within 4 conversion counts. 0 to 3.6V input range. External reference voltage input pin (AVREF) available on 128pin packages for better accuracy on low-voltage inputs. See Table 12: Operating conditions, for restrictions to the relative voltage levels of VDDQ, AVDD, AVREF, and AVREF_AVDD. CPU Firmware may convert one ADC input channel at a time, or it has the option to set the ADC to automatically scan and convert all eight ADC input channels sequentially before signalling an end-of-conversion Automatic continuous conversion mode is available for any number of designated ADC input channels Analog watchdog mode provides automatic monitoring of any ADC input, comparing it against two programmable voltage threshold values. The ADC unit will set a flag or it will interrupt the CPU if the input voltage rises above the higher threshold, or drops below the lower threshold. The ADC unit goes to stand-by mode (very low-current consumption) after any reset event. CPU firmware may also command the ADC unit to stand-by mode at any time. ADC conversion can be started or triggered by software command as well as triggers from Timer/Counter (TIM), Motor Controller and input from external pin.

3.24.1
DMA
A programmable DMA channel may be assigned by CPU firmware to service each ADC conversion result for fast DMA single-transfer.
3.25
Standard timers (TIM) with DMA
The STR91xFA has four independent, free-running 16-bit timer/counter modules designated TIM0, TIM1, TIM2, and TIM3. Each general purpose timer/counter can be configured by firmware for a variety of tasks including; pulse width and frequency measurement (input capture), generation of waveforms (output compare and PWM), event counting, delay timing, and up/down counting.
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Functional overview
STR91xFAx32 STR91XFAX42 STR91xFAx44
Each of the four timer units have the following features:

16-bit free running timer/counter Internal timer/counter clock source from a programmable 8-bit prescale of the CCU PCLK clock output Optional external timer/counter clock source from pin P2.4 shared by TIM0/TIM1, and pin P2.5 shared by TIM2/TIM3. Frequency of these external clocks must be at least 4 times less the frequency of the internal CCU PCLK clock output. Two dedicated 16-bit Input Capture registers for measuring up to two input signals. Input Capture has programmable selection of input signal edge detection Two dedicated 16-bit Output Compare registers for generation up to two output signals PWM output generation with 16-bit resolution of both pulse width and frequency One pulse generation in response to an external event A dedicated interrupt to the CPU with five interrupt flags The OCF1 flag (Output Compare 1) from the timer can be configured to trigger an ADC conversion

3.25.1
DMA
A programmable DMA channel may be assigned by CPU firmware to service each timer/counter module TIM0 and TIM1 for fast and direct single transfers.
3.26
Three-phase induction motor controller (IMC)
The STR91xFA provides an integrated controller for variable speed motor control applications. Six PWM outputs are generated on high current drive pins P6.0 to P6.5 for controlling a three-phase AC induction motor drive circuit assembly. Rotor speed feedback is provided by capturing a tachometer input signal on pin P6.6, and an asynchronous hardware emergency stop input is available on pin P6.7 to stop the motor immediately if needed, independently of firmware.
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STR91xFAx32 STR91XFAX42 STR91xFAx44 The IMC unit has the following features:

Functional overview
Three PWM outputs generated using a 10 or 16-bit PWM counter, one for each phase U, V, W. Complimentary PWM outputs are also generated for each phase. Choice of classic or zero-centered PWM generation modes 10 or 16-bit PWM counter clock is supplied through a programmable 8-bit prescaler of the APB clock. Programmable 6 or 10-bit dead-time generator to add delay to each of the three complimentary PWM outputs 8-bit repetition counter Automatic rotor speed measurement with 16-bit resolution. Schmitt trigger tachometer input with programmable edge detection Hardware asynchronous emergency stop input A dedicated interrupt to CPU with eight flags Enhanced Motor stop output polarity configuration Double update option when PWM counter reaches the max and min values in Zerocentered mode Locking feature to prevent some control register bits from being advertently modified Trigger output to start an ADC conversion
3.27
External memory interface (EMI)
STR91xFA devices in 128-pin and 144-ball packages offer an external memory bus for connecting external parallel peripherals and memories. The EMI bus resides on ports 7, 8, and 9 and operates with either an 8 or 16-bit data path. The configuration of 8 or 16 bit mode is specified by CPU firmware writing to configuration registers at run-time. If the application does not use the EMI bus, then these port pins may be used for general purpose I/O as shown in Table 9. The EMI has the following features:
Supports static asynchronous memory access cycles, including page mode for nonmux operation. The bus control signals include: - - - - EMI_RDn - read signal, x8 or x16 mode EMI_BWR_WRLn - write signal in x8 mode and write low byte signal in x16 mode EMI_WRHn - write high byte signal in x16 mode EMI_ALE - address latch signal for x8 or x16 mux bus mode with programmable polarity

Four configurable memory regions, each with a chip select output (EMI_CS0n ... EMI_CS3n) Programmable wait states per memory region for both write and read operations 16-bit multiplexed data mode (Figure 4): 16 bits of data and 16 bits of low-order address are multiplexed together on ports 8 and 9, while port 7 contains eight more high-order address signals. The output signal on pin EMI_ALE is used to demultiplex the signals on ports 8 and 9, and the polarity of EMI_ALE is programmable. The output signals on pins EMI_BWR_WRLn and EMI_WRHn are the write strobes for the low and
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Functional overview
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high data bytes respectively. The output signal EMI_RDn is the read strobe for both the low and high data bytes.
8-bit multiplexed data mode: This is a variant of the 16-bit multiplexed mode. Although this mode can provide 24 bits of address and 8 bits of data, it does require an external latch device on Port 8. However, this mode is most efficient when connecting devices that only require 8 bits of address on an 8-bit multiplexed address/data bus, and have simple read, write, and latch inputs as shown in Figure 5
To use all 24 address bits, the following applies: 8 bits of lowest-order data and 8 bits of lowest-order address are multiplexed on port 8. On port 9, 8-bits of mid-order address are multiplexed with 8 bits of data, but these 8 data values are always at logic zero on this port during a write operation, and these 8 data bits are ignored during a read operation. An external latch device (such as a `373 latch) is needed to de-multiplex the mid-order 8 address bits that are generated on port 8. Port 7 outputs the 8 highest-order address signals directly (not multiplexed). The output signal on pin EMI_ALE is used to demultiplex the signals on ports 8 and 9, and the polarity of EMI_ALE is programmable. The output signal on pin EMI_BWR_WRLn is the data write strobe, and the output on pin EMI_RDn is the data read strobe.
8-bit non-multiplexed data mode (Figure 6): Eight bits of data are on port 8, while 16 bits of address are output on ports 7 and 9. The output signal on pin EMI_BWR_BWLn is the data write strobe and the output on pin EMI_RDn is the data read strobe. Burst Mode Support (LFBGA package only): The EMI bus supports synchronized burst read and write bus cycle in multiplexed and non-multiplexed mode. The additional EMI signals in the LFBGA package that support the burst mode are: - - - - - EMI_BCLK -the bus clock output. The EMI_BCLK has the same frequency or half of that of the HCLK and can be disabled by the user EMI_WAITn - the not ready or wait input signal for synchronous access EMI_BAAn - burst address advance or burst enable signal EMI_WEn - write enable signal EMI_UBn, EMI_LBn - upper byte and lower byte enable signals. These two signals share the same pins as the EMI_WRLn and EMI_WRHn and are user configurable through the EMI register.
By defining the bus parameters such as burst length, burst type, read and write timings in the EMI control registers, the EMI bus is able to interface to standard burst memory devices. The burst timing specification and waveform will be provided in the next data sheet release
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STR91xFAx32 STR91XFAX42 STR91xFAx44 Figure 4. EMI 16-bit multiplexed connection example
STR91xx EMI_CS3n EMI_CS2n EMI_CS1n EMI_CS0n EMI_WRHn EMI_BWR_WRLn EMI_RDn EMI_ALE EMI_A23 EMI_A22 EMI_A21 EMI_A20 EMI_A19 EMI_A18 EMI_A17 EMI_A16 EMI_AD15 EMI_AD14 EMI_AD13 EMI_AD12 EMI_AD11 EMI_AD10 P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0 P9.7 P9.6 P9.5 P9.4 P9.3 P9.2 16-BIT DEVICE
Functional overview
CHIP_SELECT WRITE_HIGH_BYTE WRITE_LOW_BYTE READ ADDR_LATCH A23 A22 A21 A20 A19 A18 A17 A16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
P9.1 EMI_AD9 P9.0 EMI_AD8 EMI_AD7 P8.7
P8.6 EMI_AD6 P8.5 EMI_AD5 P8.4 EMI_AD4 P8.3 EMI_AD3 P8.2 EMI_AD2 P8.1 EMI_AD1 P8.0 EMI_AD0
Figure 5.
EMI 8-bit multiplexed connection example
ST R91xx EMI_CS3n EMI_CS2n EMI_CS1n EMI_CS0n EMI_BWR_WRLn EMI_RDn EMI_ALE EMI_AD7 EMI_AD6 EMI_AD5 EMI_AD4 EMI_AD3 EMI_AD2 EMI_AD1 EMI_AD0 P8.7 P8.6 P8.5 P8.4 P8.3 P8.2 P8.1 P8.0 8-BIT DEVICE
CHIP_SELECT WRIT E READ ADDR_LAT CH AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0
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Functional overview Figure 6.
STR91xFAx32 STR91XFAX42 STR91xFAx44 EMI 8-bit non-multiplexed connection example
STR91xx EMI_CS3n EMI_CS2n EMI_CS1n EMI_CS0n 8-BIT DEVICE
CHIP_SELECT
EMI_BWR_WRLn EMI_RDn
WRITE READ
EMI_A15 EMI_A14 EMI_A13 EMI_A12 EMI_A11 EMI_A10 EMI_A9 EMI_A8 EMI_A7 EMI_A6 EMI_A5 EMI_A4 EMI_A3 EMI_A2 EMI_A1 EMI_A0 EMI_D7 EMI_D6 EMI_D5 EMI_D4 EMI_D3 EMI_D2 EMI_D1 EMI_D0
P9.7 P9.6 P9.5 P9.4 P9.3 P9.2 P9.1 P9.0 P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0 P8.7 P8.6 P8.5 P8.4 P8.3 P8.2 P8.1 P8.0
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
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Related documentation
4
Related documentation
Available from www.arm.com: ARM966E-S Rev 2 Technical Reference Manual Available from www.st.com: STR91xFA Reference Manual STR9 Flash Programming Manual (PM0020) The above is a selected list only, a full list STR91xFA application notes can be viewed at http://www.st.com.
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Pin description
STR91xFAx32 STR91XFAX42 STR91xFAx44
5
Pin description
Figure 7. STR91xFAM 80-pin package pinout
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P4.4 P4.5 P4.6 P4.7 AVREF_AVDD VSSQ VDDQ JTDO JTDI VSS VDD JTMS JTCK JTRSTn VSSQ X1_CPU X2_CPU VDDQ RESET_OUTn JRTCK
P4.3 P4.2 P4.1 P4.0 VSS_VSSQ VDDQ P2.0 P2.1 P5.0 VSS VDD P5.1 P6.2 P6.3 VDDQ VSSQ P5.2 P5.3 P6.0 P6.1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
STR91xFAM 80-pin LQFP
USBDP (1) USBDN (1) P6.7 P6.6 RESET_INn VSSQ VDDQ P6.5 P6.4 VSS VDD P5.7 P5.6 P5.5 VDDQ VSSQ P5.4 P3.7 P3.6 P3.5
1. NU (Not Used) on STR910FAM devices. Pin 59 is not connected, pin 60 must be pulled up by a 1.5Kohm resistor to VDDQ. 2. No USBCLK function on STR910FAM devices.
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P2.2 P2.3 P2.4 VBATT VSSQ X2_RTC X1_RTC VDDQ P2.5 VSS VDD P2.6 (2) USBCLK_P.27 P3.0 VSSQ VDDQ P3.1 P3.2 P3.3 P3.4
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
STR91xFAx32 STR91XFAX42 STR91xFAx44 Figure 8. STR91xFAW 128-pin package pinout
Pin description
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
P4.3 P4.4 P4.5 P4.6 P4.7 AVREF AVDD VSSQ VDDQ P7.7 P7.6 JTDO P1.7 JTDI P1.6 VSS VDD JTMS P1.5 P1.4 JTCK JTRSTn P1.3 VSSQ X1_CPU X2_CPU VDDQ P1.2 RESET_OUTn P1.1 P1.0 JRTCK
P4.2 P4.1 P4.0 AVSS P7.0 P7.1 P7.2 VSSQ VDDQ P2.0 P2.1 P5.0 P7.3 P7.4 P7.5 VSS VDD P5.1 P6.2 P6.3 EMI_BWR_WRLn EMI_WRHn VDDQ VSSQ (3) PHYCLK_P5.2 P8.0 P5.3 P8.1 P6.0 P8.2 P6.1 P8.3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
STR91xFAW
128-pin LQFP
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
USBDP (1) USBDN (1) MII_MDIO (1) P6.7 P6.6 TAMPER_IN P0.7 RESET_INn P0.6 VSSQ VDDQ P0.5 P6.5 P6.4 VSS VDD P5.7 P5.6 P0.4 P5.5 P0.3 EMI_RDn EMI_ALE VDDQ VSSQ P0.2 P5.4 P0.1 P3.7 P0.0 P3.6 P3.5
1. NU (Not Used) on STR910FAW devices. Pin 95 is not connected, pin 96 must be pulled up by a 1.5Kohm resistor to VDDQ. 2. No USBCLK function on STR910FAW devices. 3. No PHYCLK function on STR910FAW devices.
P2.2 P8.4 P2.3 P8.5 P2.4 P8.6 VBATT VSSQ X2_RTC X1_RTC VDDQ P8.7 P2.5 P9.0 P9.1 VSS VDD P9.2 P9.3 P9.4 P2.6 (2) USBCLK_P2.7 P3.0 VSSQ VDDQ P9.5 P3.1 P3.2 P3.3 P9.6 P3.4 P9.7
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
43/99
Pin description
STR91xFAx32 STR91XFAX42 STR91xFAx44
5.1
LFBGA144 ball connections
In Table 8 balls labelled NC are no connect balls. These NC balls are reserved for future devices and should NOT be connected to ground or any other signal. There are total of 9 NC (no connection) balls. Balls H1 and G4 are assigned as EMI bus write signals (EMI_BWR_WRLn and EMI_WRHn). These two balls can also be configured by the user as EMI low or high byte select signals (EMI_LBn and EMI_UBn). The PLLGND (B8) and PLLVDDQ (C9) balls can be connected to VSSQ and VDDQ.
Table 8.
A
STR91x LFBGA144 Ball Connections
B C D E F G H EMI_WR Hn (EMI_UB n) P5.3 P8.1 P6.0 VSS P9.4 VDDQ EMI_BAA n P5.6 P0.4 P5.5 P0.3 J K L M
1
P4.2
P7.2
NC
P7.0
VDDQ
P7.3
P7.4
VDDQ
PHYCLK _P5.2(1) P8.3 P2.3 VSSQ P8.7 P9.2 P3.0 EMI_WAI Tn P9.7 P0.1 P3.7 VDDQ
P8.0
P2.2
2 3 4 5 6 7 8 9 10 11 12
AVREF AVDD P4.6 P7.7 JTMS P1.5 VSSQ RESET_ OUTn X1_CPU X2_CPU EMI_WE n
P4.1 P4.3 P4.5 VDDQ JTDO P1.4 PLLVSS Q P1.2 P1.0 JRTCK P0.7
P4.0 AVSS P4.4 VSSQ JTDI NC P1.3 PLLVDDQ P1.1 USBDP(2) RESET_I Nn
P7.1 NC VSSQ P4.7 P1.7 VDD JRSTn VDDQ USBDN
(3)
P2.0 P2.1 P5.0 P7.5 P7.6 VSS JTCK P6.6 TAMPER _ IN P0.6 NC
NC VSS VDD NC P5.1 P1.6 VSSQ VDDQ NC P0.5 NC
P6.2 P6.3 EMI_BWR _WRLn (EMI_LBn) VSSQ P2.6 P6.5 P6.4 NC VSS VDD P5.7
P8.2 P6.1 P8.5 P2.5 P9.3 VSSQ P3.3 EMI_RDn EMI_ALE P0.2 P5.4
VSSQ P8.4 P2.4 VDDQ VDD USBCLK _P2.7 (2) P9.5 P3.4 P3.5 P0.0 VSSQ
P8.6 VBATT X2_RTC X1_RTC P9.0 P9.1 EMI_BCL K P9.6 P3.1 P3.2 P3.6
MII_MDI O (3) P6.7
1. No PHYCLK function on STR910FAW devices. 2. No USBCLK function on STR910FAW devices.
3. NU (Not Used) on STR910FAW devices. D10 is not connected, C11 must be pulled up by a 1.5 kOhm resistor to VDDQ.
44/99
STR91xFAx32 STR91XFAX42 STR91xFAx44
Pin description
5.2
Default pin functions
During and just after reset, all pins on ports 0-9 default to high-impedance input mode until CPU firmware assigns other functions to the pins. This initial input mode routes all pins on ports 0-9 to be read as GPIO inputs as shown in the "Default Pin Function" column of Table 9. Simultaneously, certain port pin signals are also routed to other functional inputs as shown in the "Default Input Function" column of Table 9, and these pin input functions will remain until CPU firmware makes other assignments. At any time, even after the CPU assigns pins to alternate functions, the CPU may always read the state of any pin on ports 0-9 as a GPIO input. CPU firmware may assign alternate functions to port pins as shown in columns "Alternate Input 1" or "Alternate Output 1, 2, 3" of Table 9 by writing to control registers at run-time.
5.2.1
Note: 1
General notes on pin usage
STMicroelectronics advises to ground, or pull up to VDDQ using a 100 K resistor, all unused pins on port 0 - 9 to reduce noise susceptibility, noise generation, and minimize power consumption. There are no internal or programmable pull-up resistors on ports 0-9. All pins on ports 0 - 9 are 5V tolerant Pins on ports 0,1,2,4,5,7,8,9 have 4 mA drive and 4mA sink. Ports 3 and 6 have 8 mA drive and 8 mA sink. For 8-bit non-muxed EMI operation: Port 8 is eight bits of data, ports 7 and 9 are 16 bits of address. For 16-bit muxed EMI operation: Ports 8 and 9 are 16 bits of muxed address and data bits, port 7 is up to eight additional bits of high-order address Signal polarity is programmable for interrupt request inputs, EMI_ALE, timer input capture inputs and output compare/PWM outputs, motor control tach and emergency stop inputs, and motor control phase outputs. HiZ = High Impedance, V = Voltage Source, G = Ground, I/O = Input/Output STR910FA devices do not support USB. On these devices USBDP and USBDN signals are "Not Used" (USBDN is not connected, USBDP must be pulled up by a 1.5K ohm resistor to VDDQ), and all functions named "USB" are not available. STR910FA 128-pin and 144-ball devices do not support Ethernet. On these devices PHYCLK and all functions named "MII*" are not available. Device pin description
Signal Type Alternate functions Default Pin Function Default Input Function
2 3 4 5 6
7 8
9
Table 9.
Pkg LFBGA144 LQFP128 LQFP80
Pin Name
Alternate Input 1
I2C0_CLKIN, I2C clock in I2C0_DIN, I2C data in I2C1_CLKIN, I2C clock in I2C1_DIN, I2C data in
Alternate Output 1
GPIO_0.0, GP Output GPIO_0.1, GP Output GPIO_0.2, GP Output GPIO_0.3, GP Output
Alternate Output 2
I2C0_CLKOUT, I2C clock out I2C0_DOUT, I2C data out I2C1_CLKOUT, I2C clock out I2C1_DOUT, I2C data out
Alternate Output 3
ETM_PCK0, ETM Packet ETM_PCK1, ETM Packet ETM_PCK2, ETM Packet ETM_PCK3, ETM Packet
-
67
L11
P0.0
I/O
GPIO_0.0, GP Input, HiZ GPIO_0.1, GP Input, HiZ GPIO_0.2, GP Input, HiZ GPIO_0.3, GP Input, HiZ
MII_TX_CLK, PHY Xmit clock MII_RXD0, PHY Rx data0 MII_RXD1, PHY Rx data
-
69
K10
P0.1
I/O
-
71
J11
P0.2
I/O
-
76
H12
P0.3
I/O
45/99
Pin description Table 9.
Pkg LFBGA144 LQFP128 LQFP80 Pin Name
STR91xFAx32 STR91XFAX42 STR91xFAx44
Device pin description (continued)
Signal Type Alternate functions Default Pin Function Default Input Function
Alternate Input 1
TIM0_ICAP1, Input Capture TIM0_ICAP2, Input Capture TIM2_ICAP1, Input Capture TIM2_ICAP2, Input Capture
Alternate Output 1
GPIO_0.4, GP Output GPIO_0.5, GP Output GPIO_0.6, GP Output GPIO_0.7, GP Output
Alternate Output 2
EMI_CS0n, EMI Chip Select EMI_CS1n, EMI Chip Select EMI_CS2n, EMI Chip Select EMI_CS3n, EMI Chip Select
Alternate Output 3
ETM_PSTAT0, ETM pipe status ETM_PSTAT1, ETM pipe status ETM_PSTAT2, ETM pipe status ETM_TRSYNC, ETM trace sync
-
78
H10
P0.4
I/O
GPIO_0.4, GP Input, HiZ GPIO_0.5, GP Input, HiZ GPIO_0.6, GP Input, HiZ GPIO_0.7, GP Input, HiZ
MII_RXD2, PHY Rx data MII_RXD3, PHY Rx data MII_RX_CLK, PHY Rx clock MII_RX_DV, PHY data valid
-
85
F11
P0.5
I/O
-
88
E11
P0.6
I/O
-
90
B12
P0.7
I/O
-
98
B10
P1.0
I/O
GPIO_1.0, GP Input, HiZ GPIO_1.1, GP Input, HiZ GPIO_1.2, GP Input, HiZ GPIO_1.3, GP Input, HiZ GPIO_1.4, GP Input, HiZ GPIO_1.5, GP Input, HiZ GPIO_1.6, GP Input, HiZ GPIO_1.7, GP Input, HiZ
MII_RX_ER, PHY rcv error -
ETM_EXTRIG, ETM ext. trigger UART1_RX, UART rcv data SSP1_MISO, SSP mstr data in UART2_RX, UART rcv data I2C0_CLKIN, I2C clock in CAN_RX, CAN rcv data I2C0_DIN, I2C data in ETM_EXTRIG, ETM ext. trigger
GPIO_1.0, GP Output GPIO_1.1, GP Output GPIO_1.2, GP Output GPIO_1.3, GP Output GPIO_1.4, GP Output GPIO_1.5, GP Output GPIO_1.6, GP Output GPIO_1.7, GP Output
UART1_TX, UART xmit data MII_TXD0, MAC Tx data MII_TXD1, MAC Tx data MII_TXD2, MAC Tx data MII_TXD3, MAC Tx data UART2_TX, UART xmit data CAN_TX, CAN Tx data MII_MDC, MAC mgt dat ck
SSP1_SCLK, SSP mstr clk out SSP1_MOSI, SSP mstr dat out UART0_TX, UART xmit data SSP1_NSS, SSP mstr sel out I2C0_CLKOUT, I2C clock out ETM_TRCLK, ETM trace clock I2C0_DOUT, I2C data out ETM_TRCLK, ETM trace clock
-
99
C10
P1.1
I/O
-
101
B9
P1.2
I/O
-
-
106
C8
P1.3
I/O
-
-
109
B7
P1.4
I/O
MII_COL, PHY collision MII_CRS, PHY carrier sns -
-
110
A7
P1.5
I/O
-
114
F7
P1.6
I/O
-
116
D6
P1.7
I/O
7
10
E2
P2.0
I/O
GPIO_2.0, GP Input, HiZ GPIO_2.1, GP Input, HiZ GPIO_2.2, GP Input, HiZ GPIO_2.3, GP Input, HiZ GPIO_2.4, GP Input, HiZ GPIO_2.5, GP Input, HiZ GPIO_2.6, GP Input, HiZ GPIO_2.7, GP Input, HiZ
UART0_CTS, Clear To Send UART0_DSR, Data Set Ready UART0_DCD, Dat Carrier Det UART0_RI, Ring Indicator EXTCLK_T0T1E xt clk timer0/1 EXTCLK_T2T3E xt clk timer2/3 USB_CLK48M, 48MHz to USB
I2C0_CLKIN, I2C clock in I2C0_DIN, I2C data in I2C1_CLKIN, I2C clock in I2C1_DIN, I2C data in SSP0_SCLK, SSP slv clk in SSP0_MOSI, SSP slv dat in SSP0_MISO, SSP mstr data in SSP0_NSS, SSP slv sel in
GPIO_2.0, GP Output GPIO_2.1, GP Output GPIO_2.2, GP Output GPIO_2.3, GP Output GPIO_2.4, GP Output GPIO_2.5, GP Output GPIO_2.6, GP Output GPIO_2.7, GP Output
I2C0_CLKOUT, I2C clock out I2C0_DOUT, I2C data out I2C1_CLKOUT, I2C clock out I2C1_DOUT, I2C data out SSP0_SCLK, SSP mstr clk out SSP0_MOSI, SSP mstr dat out SSP0_MISO, SSP slv data out SSP0_NSS, SSP mstr sel out
ETM_PCK0, ETM Packet ETM_PCK1, ETM Packet ETM_PCK2, ETM Packet ETM_PCK3, ETM Packet ETM_PSTAT0, ETM pipe status ETM_PSTAT1, ETM pipe status ETM_PSTAT2, ETM pipe status ETM_TRSYNC, ETM trace sync
8
11
E3
P2.1
I/O
21
33
M1
P2.2
I/O
22
35
K3
P2.3
I/O
23
37
L4
P2.4
I/O
29
45
J5
P2.5
I/O
32
53
G6
P2.6 USBCLK _P2.7
I/O
33
54
L7
I/O
46/99
STR91xFAx32 STR91XFAX42 STR91xFAx44 Table 9.
Pkg LFBGA144 LQFP128 LQFP80 Pin Name
Pin description
Device pin description (continued)
Signal Type Alternate functions Default Pin Function Default Input Function
Alternate Input 1
UART0_RxD, UART rcv data UART2_RxD, UART rcv data UART1_RxD, UART rcv data CAN_RX, CAN rcv data SSP1_SCLK, SSP slv clk in SSP1_MISO, SSP mstr data in SSP1_MOSI, SSP slv dat in SSP1_NSS, SSP slv select in
Alternate Output 1
GPIO_3.0, GP Output GPIO_3.1, GP Output GPIO_3.2, GP Output GPIO_3.3, GP Output GPIO_3.4, GP Output GPIO_3.5, GP Output GPIO_3.6, GP Output GPIO_3.7, GP Output
Alternate Output 2
UART2_TX, UART xmit data UART0_TX, UART xmit data CAN_TX, CAN Tx data UART1_TX, UART xmit data SSP1_SCLK, SSP mstr clk out SSP1_MISO, SSP slv data out SSP1_MOSI, SSP mstr dat out SSP1_NSS, SSP mstr sel out
Alternate Output 3
TIM0_OCMP1, Out comp/PWM TIM1_OCMP1, Out comp/PWM UART0_DTR, Data Trmnl Rdy UART0_RTS, Ready To Send UART0_TX, UART xmit data UART2_TX, UART xmit data CAN_TX, CAN Tx data TIM1_OCMP1, Out comp/PWM
34
55
K7
P3.0
I/O
GPIO_3.0, GP Input, HiZ GPIO_3.1, GP Input, HiZ GPIO_3.2, GP Input, HiZ GPIO_3.3, GP Input, HiZ GPIO_3.4, GP Input, HiZ GPIO_3.5, GP Input, HiZ GPIO_3.6, GP Input, HiZ GPIO_3.7, GP Input, HiZ
DMA_RQST0, Ext DMA requst DMA_RQST1, Ext DMA requst EXINT2, External Intr EXINT3, External Intr EXINT4, External Intr EXINT5, External Intr EXINT6, External Intr EXINT7, External Intr
37
59
M10
P3.1
I/O
38
60
M11
P3.2
I/O
39
61
J8
P3.3
I/O
40
63
L9
P3.4
I/O
41
65
L10
P3.5
I/O
42
66
M12
P3.6
I/O
43
68
K11
P3.7
I/O
4
3
C2
P4.0
I/O
GPIO_4.0, GP Input, HiZ GPIO_4.1, GP Input, HiZ GPIO_4.2, GP Input, HiZ GPIO_4.3, GP Input, HiZ GPIO_4.4, GP Input, HiZ GPIO_4.5, GP Input, HiZ GPIO_4.6, GP Input, HiZ GPIO_4.7, GP Input, HiZ
ADC0, ADC input chnl ADC1, ADC input chnl ADC2, ADC input chnl ADC3, ADC input chnl ADC4, ADC input chnl ADC5, ADC input chnl ADC6, ADC input chnl ADC7, ADC input chnl /ADC Ext. trigger
TIM0_ICAP1, Input Capture TIM0_ICAP2, Input Capture TIM1_ICAP1, Input Capture TIM1_ICAP2, Input Capture TIM2_ICAP1, Input Capture TIM2_ICAP2, Input Capture TIM3_ICAP1, Input Capture TIM3_ICAP2, Input Capture
GPIO_4.0, GP Output GPIO_4.1, GP Output GPIO_4.2, GP Output GPIO_4.3, GP Output GPIO_4.4, GP Output GPIO_4.5, GP Output GPIO_4.6, GP Output GPIO_4.7, GP Output
TIM0_OCMP1, Out comp/PWM TIM0_OCMP2, Out comp TIM1_OCMP1, Out comp/PWM TIM1_OCMP2, Out comp TIM2_OCMP1, Out comp/PWM TIM2_OCMP2, Out comp TIM3_OCMP1, Out comp/PWM TIM3_OCMP2, Out comp
ETM_PCK0, ETM Packet ETM_PCK1, ETM Packet ETM_PCK2, ETM Packet ETM_PCK3, ETM Packet ETM_PSTAT0, ETM pipe status ETM_PSTAT1, ETM pipe status ETM_PSTAT2, ETM pipe status ETM_TRSYNC, ETM trace sync
3
2
B2
P4.1
I/O
2
1
A1
P4.2
I/O
1
128
B3
P4.3
I/O
80
127
C4
P4.4
I/O
79
126
B4
P4.5
I/O
78
125
A4
P4.6
I/O
77
124
D5
P4.7
I/O
9
12
E4
P5.0
I/0
GPIO_5.0, GP Input, HiZ GPIO_5.1, GP Input, HiZ GPIO_5.2, GP Input, HiZ GPIO_5.3, GP Input, HiZ GPIO_5.4, GP Input, HiZ
EXINT8, External Intr EXINT9, External Intr EXINT10, External Intr EXINT11, External Intr EXINT12, External Intr
CAN_RX, CAN rcv data UART0_RxD, UART rcv data UART2_RxD, UART rcv data ETM_EXTRIG, ETM ext. trigger SSP0_SCLK, SSP slv clk in
GPIO_5.0, GP Output GPIO_5.1, GP Output GPIO_5.2, GP Output GPIO_5.3, GP Output GPIO_5.4, GP Output
ETM_TRCLK, ETM trace clock CAN_TX, CAN Tx data MII_PHYCLK, 25Mhz to PHY MII_TX_EN, MAC xmit enbl SSP0_SCLK, SSP mstr clk out
UART0_TX, UART xmit data UART2_TX, UART xmit data TIM3_OCMP1, Out comp/PWM TIM2_OCMP1, Out comp/PWM EMI_CS0n, EMI Chip Select
12
18
F6
P5.1 PHYCLK _P5.2 P5.3
I/0
17
25
K1
I/O
18
27
H2
I/O
44
70
J12
P5.4
I/O
47/99
Pin description Table 9.
Pkg LFBGA144 LQFP128 LQFP80 Pin Name
STR91xFAx32 STR91XFAX42 STR91xFAx44
Device pin description (continued)
Signal Type Alternate functions Default Pin Function Default Input Function
Alternate Input 1
SSP0_MOSI, SSP slv dat in SSP0_MISO, SSP mstr dat in SSP0_NSS, SSP slv select in
Alternate Output 1
GPIO_5.5, GP Output GPIO_5.6, GP Output GPIO_5.7, GP Output
Alternate Output 2
SSP0_MOSI, SSP mstr dat out SSP0_MISO, SSP slv data out SSP0_NSS, SSP mstr sel out
Alternate Output 3
EMI_CS1n, EMI Chip Select EMI_CS2n, EMI Chip Select EMI_CS3n, EMI Chip Select
47
77
H11
P5.5
I/O
GPIO_5.5, GP Input, HiZ GPIO_5.6, GP Input, HiZ GPIO_5.7, GP Input, HiZ
EXINT13, External Intr EXINT14, External Intr EXINT15, External Intr
48
79
H9
P5.6
I/O
49
80
G12
P5.7
I/O
19
29
H4
P6.0
I/O
GPIO_6.0, GP Input, HiZ GPIO_6.1, GP Input, HiZ GPIO_6.2, GP Input, HiZ GPIO_6.3, GP Input, HiZ GPIO_6.4, GP Input, HiZ GPIO_6.5, GP Input, HiZ GPIO_6.6, GP Input, HiZ GPIO_6.7, GP Input, HiZ
EXINT16, External Intr EXINT17, External Intr EXINT18, External Intr EXINT19, External Intr EXINT20, External Intr EXINT21, External Intr EXINT22_TRIG, Ext Intr & Tach EXINT23_STOP, Ext Intr & Estop
TIM0_ICAP1, Input Capture TIM0_ICAP2, Input Capture TIM1_ICAP1, Input Capture TIM1_ICAP2, Input Capture TIM2_ICAP1, Input Capture TIM2_ICAP2, Input Capture UART0_RxD, UART rcv data ETM_EXTRIG, ETM ext. trigger
GPIO_6.0, GP Output GPIO_6.1, GP Output GPIO_6.2, GP Output GPIO_6.3, GP Output GPIO_6.4, GP Output GPIO_6.5, GP Output GPIO_6.6, GP Output GPIO_6.7, GP Output
TIM0_OCMP1, Out comp/PWM TIM0_OCMP2, Out comp TIM1_OCMP1, Out comp/PWM TIM1_OCMP2, Out comp TIM2_OCMP1, Out comp/PWM TIM2_OCMP2, Out comp TIM3_OCMP1, Out comp/PWM TIM3_OCMP2, Out comp
MC_UH, IMC phase U hi MC_UL, IMC phase U lo MC_VH, IMC phase V hi MC_VL, IMC phase V lo MC_WH, IMC phase W hi MC_WL, IMC phase W lo ETM_TRCLK, ETM trace clock UART0_TX, UART xmit data
20
31
J3
P6.1
I/O
13
19
G2
P6.2
I/O
14
20
G3
P6.3
I/O
52
83
G8
P6.4
I/O
53
84
G7
P6.5
I/O
57
92
E9
P6.6
I/O
58
93
D12
P6.7
I/O
-
5
D1
P7.0
I/O
GPIO_7.0, GP Input, HiZ GPIO_7.1, GP Input, HiZ GPIO_7.2, GP Input, HiZ GPIO_7.3, GP Input, HiZ GPIO_7.4, GP Input, HiZ GPIO_7.5, GP Input, HiZ GPIO_7.6, GP Input, HiZ GPIO_7.7, GP Input, HiZ
EXINT24, External Intr EXINT25, External Intr EXINT26, External Intr EXINT27, External Intr EXINT28, External Intr EXINT29, External Intr EXINT30, External Intr EXINT31, External Intr
TIM0_ICAP1, Input Capture TIM0_ICAP2, Input Capture TIM2_ICAP1, Input Capture TIM2_ICAP2, Input Capture UART0_RxD, UART rcv data ETM_EXTRIG, ETM ext. trigger TIM3_ICAP1, Input Capture TIM3_ICAP2, Input Capture
GPIO_7.0, GP Output GPIO_7.1, GP Output GPIO_7.2, GP Output GPIO_7.3, GP Output GPIO_7.4, GP Output GPIO_7.5, GP Output GPIO_7.6, GP Output GPIO_7.7, GP Output
8b) EMI_A0, 16b) EMI_A16 8b) EMI_A1, 16b) EMI_A17 8b) EMI_A2, 16b) EMI_A18 8b) EMI_A3, 16b) EMI_A19 8b) EMI_A4, 16b) EMI_A20 8b) EMI_A5, 16b) EMI_A21 8b) EMI_A6, 16b) EMI_A22 EMI_CS0n, EMI chip select
ETM_PCK0, ETM Packet ETM_PCK1, ETM Packet ETM_PCK2, ETM Packet ETM_PCK3, ETM Packet EMI_CS3n, EMI Chip Select EMI_CS2n, EMI Chip Select EMI_CS1n, EMI Chip Select 16b) EMI_A23, 8b) EMI_A7
-
6
D2
P7.1
I/O
-
7
B1
P7.2
I/O
-
13
F1
P7.3
I/O
-
14
G1
P7.4
I/O
-
15
E5
P7.5
I/O
-
118
E6
P7.6
I/O
-
119
A5
P7.7
I/O
-
26
L1
P8.0
I/O
GPIO_8.0, GP Input, HiZ
-
-
GPIO_8.0, GP Output
8b) EMI_D0, 16b) EMI_AD0
-
48/99
STR91xFAx32 STR91XFAX42 STR91xFAx44 Table 9.
Pkg LFBGA144 LQFP128 LQFP80 Pin Name
Pin description
Device pin description (continued)
Signal Type Alternate functions Default Pin Function Default Input Function
Alternate Input 1
Alternate Output 1
GPIO_8.1, GP Output GPIO_8.2, GP Output GPIO_8.3, GP Output GPIO_8.4, GP Output GPIO_8.5, GP Output GPIO_8.6, GP Output GPIO_8.7, GP Output
Alternate Output 2
8b) EMI_D1, 16b) EMI_AD1 8b) EMI_D2, 16b) EMI_AD2 8b) EMI_D3, 16b) EMI_AD3 8b) EMI_D4, 16b) EMI_AD4 8b) EMI_D5, 16b) EMI_AD5 8b) EMI_D6, 16b) EMI_AD6 8b) EMI_D7, 16b) EMI_AD7
Alternate Output 3
-
28
H3
P8.1
I/O
GPIO_8.1, GP Input, HiZ GPIO_8.2, GP Input, HiZ GPIO_8.3, GP Input, HiZ GPIO_8.4, GP Input, HiZ GPIO_8.5, GP Input, HiZ GPIO_8.6, GP Input, HiZ GPIO_8.7, GP Input, HiZ
-
-
-
-
30
J2
P8.2
I/O
-
-
-
-
32
K2
P8.3
I/O
-
-
-
-
34
L3
P8.4
I/O
-
-
-
-
36
J4
P8.5
I/O
-
-
-
-
38
M2
P8.6
I/O
-
-
-
-
44
K5
P8.7
I/O
-
-
-
-
46
M6
P9.0
I/O
GPIO_9.0, GP Input, HiZ GPIO_9.1, GP Input, HiZ GPIO_9.2, GP Input, HiZ GPIO_9.3, GP Input, HiZ GPIO_9.4, GP Input, HiZ GPIO_9.5, GP Input, HiZ GPIO_9.6, GP Input, HiZ GPIO_9.7, GP Input, HiZ
-
-
GPIO_9.0, GP Output GPIO_9.1, GP Output GPIO_9.2, GP Output GPIO_9.3, GP Output GPIO_9.4, GP Output GPIO_9.5, GP Output GPIO_9.6, GP Output GPIO_9.7, GP Output
8b) EMI_A8 16b) EMI_AD8 8b) EMI_A9, 16b) EMI_AD9 8b) EMI_A10, 16b)EMI_AD10 8b) EMI_A11, 16b)EMI_AD11 8b) EMI_A12, 16b)EMI_AD12 8b) EMI_A13, 16b)EMI_AD13 8b) EMI_A14, 16b)EMI_AD14 8b) EMI_A15, 16b)EMI_AD15
-
-
47
M7
P9.1
I/O
-
-
-
-
50
K6
P9.2
I/O
-
-
-
-
51
J6
P9.3
I/O
-
-
-
-
52
H6
P9.4
I/O
-
-
-
-
58
L8
P9.5
I/O
-
-
-
-
62
M9
P9.6
I/O
-
-
-
-
64
K9
P9.7
I/O
-
-
-
-
21
G4
EMI_BW R _WRLn
O
EMI byte write strobe (8 bit mode) or low byte write strobe (16 bit mode) Can also be configured as EMI_LBn in BGA package EMI high byte write strobe (16-bit mode) Can also be configured as EMI_UBn in BGA package
N/A
-
22
H1
EMI_WR Hn
O
N/A
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Pin description Table 9.
Pkg LFBGA144 LQFP128 LQFP80 Pin Name
STR91xFAx32 STR91XFAX42 STR91xFAx44
Device pin description (continued)
Signal Type Alternate functions Default Pin Function Default Input Function
Alternate Input 1
Alternate Output 1
Alternate Output 2
Alternate Output 3
-
74
J10
EMI_ALE
O
EMI address latch enable (mux mode) EMI read strobe EMI Burst address advance EMI Wait input for burst mode device EMI bus clock EMI write enable Tamper detection input MAC/PHY management data line USB data (-) bus connect USB data (+) bus connect External reset input Global or System reset output CPU oscillator or crystal input CPU crystal connection RTC oscillator or crystal input (32.768 kHz) RTC crystal connection JTAG return clock or RTC clock JTAG TAP controller reset JTAG clock JTAG mode select JTAG data in JTAG data out
N/A
-
75
J9
EMI_RDn EMI_BAA n EMI_WAI Tn EMI_BCL K EMI_WE n TAMPER _IN MII_MDI O USBDN USBDP RESET _INn RESET _OUTn X1_CPU X2_CPU
O
N/A
-
-
H8
O
N/A
-
-
K8
I
N/A
-
91
M8 A12 E10
O O I
N/A N/A N/A
-
94
D11
I/O
N/A
59 60 56
95 96 89
D10 C11 C12
I/O I/O I
N/A N/A N/A
62
100
A9
O
N/A
65 64
104 103
A10 A11
I O
N/A N/A
27
42
M5
X1_RTC
I
N/A
26
41
M4
X2_RTC
O
N/A
61
97
B11
JRTCK
O
N/A
67 68 69 72 73
107 108 111 115 117
D8 E8 A6 C6 B6
JTRSTn JTCK JTMS JTDI JTDO
I I I I O
N/A N/A N/A N/A N/A
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STR91xFAx32 STR91XFAX42 STR91xFAx44 Table 9.
Pkg LFBGA144 LQFP128 LQFP80 Pin Name
Pin description
Device pin description (continued)
Signal Type Alternate functions Default Pin Function Default Input Function
Alternate Input 1
Alternate Output 1
Alternate Output 2
Alternate Output 3
-
122
A3
AVDD
V
ADC analog voltage source, 2.7V - 3.6V ADC analog ground Common ground point for digital I/O & analog ADC ADC reference voltage input Combined ADC ref voltage and ADC analog voltage source, 2.7V - 3.6V Standby voltage input for RTC and SRAM backup
N/A
-
4
C3
AVSS
G
N/A
5
-
-
AVSS _VSSQ
G
N/A
-
123
A2
AVREF
V
N/A
76
-
-
AVREF _AVDD
V
N/A
24
39
M3
VBATT
V
N/A
6 15 36 46 54 28 63 74 16 35 45 55 25 66 75
9 23 57 73 86 43 102 120 8 24 56 72 87 40 105 121
E1 J1 K12 B5 L5 H7 D9 F9 L2 K4 C5 D4 G5 J7 A8 F8 L12
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
V V V V V V V V V G G G G G G G G G Digital Ground for !/O and USB N/A V Source for I/O and USB. 2.7V to 3.6V
N/A
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Pin description Table 9.
Pkg LFBGA144 LQFP128 LQFP80 Pin Name
STR91xFAx32 STR91XFAX42 STR91xFAx44
Device pin description (continued)
Signal Type Alternate functions Default Pin Function Default Input Function
Alternate Input 1
Alternate Output 1
Alternate Output 2
Alternate Output 3
11 31 50 70 10 30 51 71 -
17 49 81 112 16 48 82 113 -
F4 D7 L6 G11 F3 H5 G10 E7 C9
VDD VDD VDD VDD VSS VSS VSS VSS PLLVDD Q PLLVSSQ
V V V V G G G G V V Source for PLL 2.7 to 3.6 V Digital Ground for PLL Digital Ground for CPU N/A V Source for CPU. 1.65V - 2.0V N/A
N/A
-
-
B8
G
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Memory mapping
6
Memory mapping
The ARM966E-S CPU addresses a single linear address space of 4 giga-bytes (232) from address 0x0000.0000 to 0xFFFF.FFFF as shown in Figure 9. Upon reset the CPU boots from address 0x0000.0000, which is chip-select zero at address zero in the Flash Memory Interface (FMI). The Instruction TCM and Data TCM enable high-speed CPU operation without incurring any performance or power penalties associated with accessing the system buses (AHB and APB). I-TCM and D-TCM address ranges are shown at the bottom of the memory map in Figure 9.
6.1
Buffered and non-buffered writes
The CPU makes use of write buffers on the AHB and the D-TCM to decouple the CPU from any wait states associated with a write operation. The user may choose to use write with buffers on the AHB by setting bit 3 in control register CP15 and selecting the appropriate AHB address range when writing. By default at reset, buffered writes are disabled (bit 3 of CP15 is clear) and all AHB writes are non-buffered until enabled. Figure 9 shows that most addressable items on the AHB are aliased at two address ranges, one for buffered writes and another for non-buffered writes. A buffered write will allow the CPU to continue program execution while the write-back is performed through a FIFO to the final destination on the AHB. If the FIFO is full, the CPU is stalled until FIFO space is available. A non-buffered write will impose an immediate delay to the CPU, but results in a direct write to the final AHB destination, ensuring data coherency. Read operations from AHB locations are always direct and never buffered.
6.2
System (AHB) and peripheral (APB) buses
The CPU will access SRAM, higher-speed peripherals (USB, Ethernet, Programmable DMA), and the external bus (EMI) on the AHB at their respective base addresses indicated in Figure 9. Lower-speed peripherals reside on the APB and are accessed using two separate AHB-to-APB bridge units (APB0 and APB1). These bridge units are essentially address windows connecting the AHB to the APB. To access an individual APB peripheral, the CPU will place an address on the AHB bus equal to the base address of the appropriate bridge unit APB0 or APB1, plus the offset of the particular peripheral, plus the offset of the individual data location within the peripheral. Figure 9 shows the base addresses of bridge units APB0 and APB1, and also the base address of each APB peripheral. Please consult the STR91xFA Reference manual for the address of data locations within each individual peripheral.
6.3
SRAM
The SRAM is aliased at three separate address ranges as shown in Figure 9. When the CPU accesses SRAM starting at 0x0400.0000, the SRAM appears on the D-TCM. When CPU access starts at 0x4000.0000, SRAM appears in the buffered AHB range. Beginning at CPU address 0x5000.0000, SRAM is in non-buffered AHB range. The SRAM size must be specified by CPU intitialization firmware writing to a control register after any reset condition.
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Memory mapping
STR91xFAx32 STR91XFAX42 STR91xFAx44
Default SRAM size is 32K bytes, with option to set to 64K bytes on STR91xFAx3x devices, and to 96K bytes on STR91xFAx4x devices. When other AHB bus masters (such as a DMA controller) write to SRAM, their access is never buffered. Only the CPU can make use of buffered AHB writes.
6.4
Two independent Flash memories
The STR91xFA has two independent Flash memories, the larger primary Flash and the small secondary Flash. It is possible for the CPU to erase/write to one of these Flash memories while simultaneously reading from the other. One or the other of these two Flash memories may reside at the "boot" address position of 0x0000.0000 at power-up or at reset as shown in Figure 9. The default configuration is that the first sector of primary Flash memory is enabled and residing at the boot position, and the secondary Flash memory is disabled. This default condition may be optionally changed as described below.
6.4.1
Default configuration
When the primary Flash resides at boot position, typical CPU initialization firmware would set the start address and size of the main Flash memory, and go on to enable the secondary Flash, define it's start address and size. Most commonly, firmware would place the secondary Flash start address at the location just after the end of the primary Flash memory. In this case, the primary Flash is used for code storage, and the smaller secondary flash can be used for data storage (EEPROM emulation).
6.4.2
Optional configuration
Using the STR91xFA device configuration software tool, or IDE from 3rd party, one can specify that the smaller secondary Flash memory is at the boot location at reset and the primary Flash is disabled. The selection of which Flash memory is at the boot location is programmed in a non-volatile Flash-based configuration bit during JTAG ISP. The boot selection choice will remain as the default until the bit is erased and re-written by the JTAG interface. The CPU cannot change this choice for boot Flash, only the JTAG interface has access. In this case where the secondary Flash defaults to the boot location upon reset, CPU firmware would typically initialize the Flash memories the following way. The secondary Flash start address and size is specified, then the primary Flash is enabled and its start address and size is specified. The primary Flash start address would typically be located just after the final address location of the secondary Flash. This configuration is particularly well-suited for In-Application-Programming (IAP). The CPU would boot from the secondary Flash memory, initialize the system, then check the contents of the primary Flash memory (by checksum or other means). If the contents of primary Flash is OK, then CPU execution continues from either Flash memory. If the main Flash contents are incorrect, the CPU, while executing code from the secondary Flash, can download new data from any STR91xFA communication channel and program into primary Flash memory. Application code then starts after the new contents of primary Flash are verified.
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Memory mapping
6.5
STR91xFA memory map
The memory map is shown in Figure 9: STR91xFA memory map on page 56:
Either of the two Flash memories may be placed at CPU boot address 0x0000.0000. By default, the primary Flash memory is in boot position starting at CPU address 0x0000.0000 and the secondary Flash memory may be placed at a higher address following the end of the primary Flash memory. This default option may be changed using the STR91xx device configuration software, placing the secondary Flash memory at CPU boot location 0x0000.0000, and then the primary Flash memory may be placed at a higher address. The local SRAM (64KB or 96KB) is aliased in three address windows. A) At 0x0400.0000 the SRAM is accessible through the CPU's D-TCM, at 0x4000.0000 the SRAM is accessible through the CPU's AHB in buffered accesses, and at 0x5000.0000 the SRAM is accessible through the CPU's AHB in non-buffered accesses. An AHB bus master other than the CPU can access SRAM in all three aliased windows, but these accesses are always non-buffered. The CPU is the only AHB master that can performed buffered writes. APB peripherals reside in two AHB-to-APB peripheral bridge address windows, APB0 and APB1. These peripherals are accessible with buffered AHB access if the CPU addresses them in the address range of 0x4800.0000 to 0x4FFF.FFFF, and nonbuffered access in the address range of 0x5800.0000 to 0x5FFF.FFFF. Individual peripherals on the APB are accessed at the listed address offset plus the base address of the appropriate AHB-to-APB bridge.
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Memory mapping Figure 9. STR91xFA memory map
STR91xFAx32 STR91XFAX42 STR91xFAx44
TOTAL 4 GB CPU MEMORY SPACE
0xFFFF.FFFF 0xFFFF.F000 0xFC01.0000 0xFC00.0000
APB1+0x03FF.FFFF APB1+0x0000.E000
APB BASE + OFFSET
PERIPHERAL BUS MEMORY SPACE
RESERVED
I2C1
4 KB
VIC0
4 KB
APB1+0x0000.D000
AHB NONBUFFERED
RESERVED
VIC1
64 KB
APB1+0x0000.C000 APB1+0x0000.B000 APB1+0x0000.A000 APB1+0x0000.9000
I2C0
WATCHDOG ADC CAN SSP1 SSP0 UART2 UART1 UART0 IMC SCU RTC APB1 CONFIG
4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB APB1, AHBto-APB Bridge
RESERVED
APB1+0x0000.8000 APB1+0x0000.7000 APB1+0x0000.6000
0x8000.0000 0x7C00.0000 0x7800.0000 0x7400.0000 0x7000.0000 0x6C00.0000 0x6800.0000 0x6400.0000 0x6000.0000 0x5C00.0000 0x5800.0000 0x5400.0000 0x5000.0000 0x4C00.0000 0x4800.0000 0x4400.0000 0x4000.0000 0x3C00.0000 0x3800.0000 0x3400.0000 0x3000.0000 0x2C00.0000 0x2800.0000 0x2400.0000 0x2000.0000
ENET 8-CH DMA EMI USB ENET 8-CH DMA EMI USB APB1 APB0 FMI SRAM, AHB APB1 APB0 FMI SRAM, AHB Ext. MEM, CS0 Ext. MEM, CS1 Ext. MEM, CS2 Ext. MEM, CS3 Ext. MEM, CS0 Ext. MEM, CS1 Ext. MEM, CS2 Ext. MEM, CS3
64 MB 64 MB 64 MB 64 MB 64 MB 64 MB 64 MB 64 MB 64 MB 64 MB 64 MB 64 MB 64 MB 64 MB 64 MB 64 MB 64 MB 64 MB 64 MB 64 MB 64 MB 64 MB 64 MB 64 MB AHB BUFFERED AHB NONBUFFERED AHB BUFFERED AHB NONBUFFERED
APB1+0x0000.5000 APB1+0x0000.4000 APB1+0x0000.3000 APB1+0x0000.2000 APB1+0x0000.1000 APB1+0x0000.0000 APB0+0x03FF.FFFF APB0+0x0001.0000
AHB NONBUFFERED
RESERVED
GPIO PORT P9 GPIO PORT P8 GPIO PORT P7 GPIO PORT P6 GPIO PORT P5 GPIO PORT P4 GPIO PORT P3 GPIO PORT P2 GPIO PORT P1 GPIO PORT P0 TIM3 TIM2 TIM1 TIM0 WAKE-UP UNIT APB0 CONFIG
4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB
4 KB 4 KB 4 KB 4 KB 4 KB 4 KB
PERIPHERAL BUS, NON- BUFFERED ACCESS
APB0+0x0000.F000 APB0+0x0000.E000 APB0+0x0000.D000 APB0+0x0000.C000
PERIPHERAL BUS, BUFFERED ACCESS AHB BUFFERED
APB0+0x0000.B000 APB0+0x0000.A000 APB0+0x0000.9000 APB0+0x0000.8000 APB0+0x0000.7000 APB0+0x0000.6000 APB0+0x0000.5000 APB0+0x0000.4000 APB0+0x0000.3000 APB0+0x0000.2000 APB0+0x0000.1000 APB0+0x0000.0000
APB0, AHBto-APB Bridge
Order of the two Flash memories is user defined.
RESERVED
SECONDARY FLASH (BANK 1), 32KB MAIN FLASH (BANK 0), 256KB or 512KB,
0x0000.0000
MAIN FLASH (BANK 0), 256KB or 512KB, SECONDARY FLASH (BANK 1), 32KB
OPTIONAL ORDER
0x0800.0000 0x0400.0000 0x0000.0000
SRAM, D-TCM FLASH, I-TCM
Using 64 KB or 96 KB Using 288 KB or 544 KB
DEFAULT ORDER
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STR91xFAx32 STR91XFAX42 STR91xFAx44
Electrical characteristics
7
7.1
Electrical characteristics
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
7.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TAmax (given by the selected temperature range). Data based on product characterisation, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3).
7.1.2
Typical values
Unless otherwise specified, typical data are based on TA=25 C, VDDQ=3 V and VDD=1.8 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2).
7.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
7.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10. Figure 10. Pin loading conditions
STR9 PIN
CL=50pF
7.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11.
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Electrical characteristics Figure 11. Pin input voltage
STR91xFAx32 STR91XFAX42 STR91xFAx44
STR9 PIN
VIN
7.2
Absolute maximum ratings
This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take normal precautions to avoid application of any voltage higher than the specified maximum rated voltages. It is also recommended to ground any unused input pin to reduce power consumption and minimize noise. Table 10.
Symbol VDD VDDQ VBATT AVDD AVREF AVREF_AVDD
Absolute maximum ratings
Value Parameter Min Voltage on VDD pin with respect to ground VSS Voltage on VDDQ pin with respect to ground VSS Voltage on VBATT pin with respect to ground VSS Voltage on AVDD pin with respect to ground VSS (128-pin and 144-ball packages) Voltage on AVREF pin with respect to ground VSS (128-pin and 144-ball packages) Voltage on AVREF_AVDD pin with respect to Ground VSS (80-pin package) Voltage on 5V tolerant pins with respect to ground VSS Voltage on any other pin with respect to ground VSS Storage Temperature Junction Temperature ESD Susceptibility (Human Body Model) 2000 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55 Max 2.4 4.0 4.0 4.0 4.0 4.0 5.5 4.0 +150 +125 V V V V V V V V C C V Unit
VIN
TST TJ ESD
Note:
Stresses exceeding above listed recommended "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN>VDDQ or VIN58/99
STR91xFAx32 STR91XFAX42 STR91xFAx44 Table 11.
Symbol IVDD_IO(1) IVSS_IO(1) IIO IINJ(PIN)(3) IINJ(PIN)(3)
Electrical characteristics
Current characteristics
Ratings Total current into VDD_IO power lines (source) (2) Total current out of VSS ground lines (sink)
(2)
Maximum value 200 200
Unit
mA 25 - 25 5 mA 25
Output current sunk by any I/O and control pin Output current source by any I/Os and control pin Injected current on any pin during overload condition(4) Absolute sum of all input currents during overload condition
(4)
1. The user can use GPIOs to source or sink current. In this case, the user must ensure that these absolute max. values are not exceeded (taking into account the RUN power consumption). 2. All 3.3 V or 5.0 V power (VDD_IO, VDDA_ADC, VDDA_PLL) and ground (VSS_IO, VSSA_ADC, VDDA_ADC) pins must always be connected to the external 3.3V or 5.0V supply. 3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN59/99
Electrical characteristics
STR91xFAx32 STR91XFAX42 STR91xFAx44
7.3
Operating conditions
Table 12. Operating conditions
Value Symbol VDD VDDQ VBATT(1) AVDD AVREF AVREF_AVDD TA Parameter Min Digital CPU supply voltage Digital I/O supply voltage SRAM backup and RTC supply voltage Analog ADC supply voltage (128-pin and 144-ball packages) Analog ADC reference voltage (128-pin and 144-ball packages) Combined analog ADC reference and ADC supply voltage (80-pin package) Ambient temperature under bias 1.65 2.7 2.5 2.7 2.65 2.7 -40 Max 2.0 3.6 3.6 VDDQ AVDD(2) VDDQ +85 V V V V V V C Unit
1. The VBATT pin should be connected to VDDQ if no battery is installed 2. AVREF must never exceed VDDQ
7.3.1
Operating conditions at power-up / power-down
Subject to general operating conditions for TA. Table 13.
Symbol tVDD
Operating conditions at power-up / power-down
Parameter VDD rise time rate Min(1) 10 10 Max(1) Unit s/V ms/V
1. Data guaranteed by characterization, not tested in production.
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Electrical characteristics
7.4
Table 14.
Symbol tRINMIN tPOR
RESET_INn and power-on-reset characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 C unless otherwise specified. RESET_INn and power-on-reset characteristics
Value Parameter RESET_INn Valid Active Low Power-On-Reset Condition duration RESET_OUT Duration (Watchdog reset) VDDQ,VDD ramp time is less than 10ms: 0V to VDD Test Conditions Min(1) 100 10 Unit Typ Max ns ms
tRSO
one PCLK
ns
1. Data based on bench measurements, not tested in production.
7.5
Table 15.
Symbol
LVD electrical characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 C unless otherwise specified. LVD electrical characteristics
Parameter LVD threshold during VDD rise LVD threshold during VDD fall VDD brown out warning threshold
(1)(2) (1)(2) (1)(2) (2)(3) (2)(3) (2)(3)
Test Conditions
Value Unit Min 1.43 1.33 Typ 1.50 1.40 1.65 2.32 2.23 2.45 2.35 2.65 2.61 2.52 2.75 2.65 2.95 2.89 2.78 V 2.57 V 2.46 V V Max 1.58 1.47 V V V
VDD_LVD+ (1.8V) VDD_LVD- (1.8V) VDD_BRN (1.8V)
VDDQ_LVD+ (3.0V) LVD threshold during VDDQ rise VDDQ_LVD- (3.0V) VDDQ_BRN (3.0V) LVD threshold during VDDQ fall VDDQ brown out warning threshold
VDDQ_LVD+ (3.3V) LVD threshold during VDDQ rise VDDQ_LVD- (3.3V) VDDQ_BRN (3.3V) LVD threshold during VDDQ fall VDDQ brown out warning threshold
1. For VDDQ I/O voltage operating at 2.7 - 3.3V. 2. Selection of VDDQ operation range is made using configuration software from ST, or IDE from 3rd parties. The default condition is VDDQ=2.7V - 3.3V. 3. For VDDQ I/O voltage operating at 3.0 - 3.6V.
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Electrical characteristics
STR91xFAx32 STR91XFAX42 STR91xFAx44
7.5.1
LVD delay timing
Case 1: When VDDQ reaches the VDDQ_LVD+ threshold after the first ~10 ms delay (introduced by the VDD rising edge), a new ~10 ms delay starts before the release of RESET_OUTn. See Figure 12. Figure 12. LVD reset delay case 1
VDDQ_LVD+ VDD (green) VDDQ (red) RESET_OUTn (blue) VDD_LVD+
~10 ms delay
~10 ms delay
Case 2: When VDDQ reaches the VDDQ_LVD+ threshold before the first ~10 ms delay (introduced by the VDD rising edge), RESET_OUTn will be released immediately at the end of the delay. No new delay is introduced in this case. See Figure 13. Figure 13. LVD reset delay case 2
VDDQ_LVD+ VDD_LVD+ VDD (green) VDDQ (red) RESET_OUTn (blue)
~10 ms delay
Case 3: When VDD reaches the VDD_LVD+ threshold after the VDDQ rising edge, RESET_OUTn will be released at the end of a ~10 ms delay. See Figure 14 Figure 14. LVD reset delay case 3
VDDQ_LVD+ VDD_LVD+ VDD (green) VDDQ (red) RESET_OUTn (blue)
~10 ms delay
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Electrical characteristics
7.6
Supply current characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 C unless otherwise specified. Table 16.
Symbol
Supply current characteristics
Value Parameter Test Conditions Min All peripherals CPU_CLK = on Run Mode Current 96 MHz All peripherals (1)(2) off All peripherals on (2)(3) Idle Mode Current Sleep Mode Current, IDD Sleep Mode Current, IDDQ RTC Standby Current SRAM Standby Current Typ 1.7 1.3 1.14 0.45 55 50 7 7 0.9 5 Max 2.3 mA/MHz 1.6 1.7 0.75 825 820 TBD TBD 1.2 240 mA/MHz mA/MHz A A A A A A Unit
IDDRUN
IIDLE
All peripherals off(2)(4) LVD On LVD Off LVD On
(5) (5) (4)
ISLEEP(IDD)
ISLEEP(IDDQ) IRTC_STBY ISRAM_STBY
LVD Off (4) Measured on VBATT pin Measured on VBATT pin
1. ARM core and peripherals active with all clocks on. Power can be conserved by turning off clocks to peripherals which are not required. 2. mA/MHz data valid down to 10 MHz. Below this frequency the ratio mA/MHz increases. 3. ARM core stopped and all peripheral clocks active. 4. ARM core stopped and all peripheral clocks stopped. 5. ARM core and all peripheral clocks stopped (with exception of RTC)
Figure 15. Sleep mode current vs temperature with LVD on 2000 1800 1600 1400 Idd[A] 1200 1000 800 600 400 200 -40 -20 0 0 20 40 60 80 100 120 Vcc = 2.0 V and corner process
Vcc = 1.8 V and standard process
TEMP [C]
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Electrical characteristics
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7.7
Clock and timing characteristics
Table 17.
Symbol fMSTR
Internal clock frequencies
Value Parameter CCU Master Clock Executing from SRAM Test Conditions Min 32.768 Typ Max 96,000 96 96 48 96 4 25 96 96 32.768 25 48 kHz MHz MHz MHz MHz MHz MHz MHz kHz MHz MHz Unit
fCPUCLK CPU Core Frequency
Executing from Flash
fPCLK fHCLK fOSC fFMICLK fBCLK fRTC fEMAC fUSB
Peripheral Clock for APB Peripheral Clock for AHB Clock Input FMI Flash Bus clock (internal clock) External Memory Bus clock RTC Clock EMAC PHY Clock USB Clock
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Electrical characteristics
7.7.1
Main oscillator electrical characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 C unless otherwise specified. Table 18.
Symbol
Main oscillator electrical characteristics
Value Parameter Test Conditions Min Typ 2 Max 3 mS VDD stable (1) Unit
tSTUP(OSC) Oscillator Start-up Time
1. Data characterized with quartz crystal, not tested in production.
7.7.2
X1_CPU external clock source
Subject to general operating conditions for VDD and TA. Table 19.
Symbol
External clock characteristics
Parameter External clock source frequency X1 input pin high level voltage X1 input pin low level voltage X1 high or low time(2) X1 rise or fall time(2) X1 input leakage current X1 input capacitance(2) 45 VSSVINVDD 5 55 See Figure 16 Test Conditions(1) Value Unit Min 4 0.7xVDD VSS 6 20 1 Typ Max 25 VDD 0.3xVDD MHz V V ns ns A pF %
fX1 VX1H VX1L tw(X1H) tw(X1L) tr(X1) tf(X1) IL CIN(X1)
DuCy(X1) Duty cycle
1. Data based on typical appilcation software.
2. Data based on design simulation and/or technology characteristics, not tested in production.
Figure 16. Typical application with an external clock source
90% VX1H 10%
VX1L tr(T1) tf(X1) tw(X1H) tw(X1L)
TX1
X2_CPU EXTERNAL CLOCK SOURCE hi-Z X1_CPU IL
fOSC
STR91xF
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Electrical characteristics
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7.7.3
RTC oscillator electrical characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 C unless otherwise specified. Table 20.
Symbol gM(RTC)
RTC oscillator electrical characteristics
Parameter Oscillator Start _voltage(1)
(1)
Test Conditions
Value Unit Min
VDD_LVD+ (2)
Typ
Max V 1 S
tSTUP(RTC) Oscillator Start-up Time
VDD stable
1. Data based on bench measurements, not tested in production. 2. Refer to Table 15 for min. value of VDD_LVD+
Table 21.
Symbol fO RS CL
RTC crystal electrical characteristics
Value Parameter Min Resonant frequency Series resistance Load capacitance 8 Typ 32.768 40 Max kHz k pF Unit
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Electrical characteristics
7.7.4
PLL electrical characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 C unless otherwise specified. Table 22.
Symbol fPLL fOSC tLOCK
PLL electrical characteristics
Value Parameter Min PLL Output Clock Clock Input PLL lock time PLL Jitter (peak to peak)(1) 6.25 4 300 0.1 Typ Max 96 25 1500 0.2 MHz MHz s ns Unit
tJITTER
1. Data based on bench measurements, not tested in production
7.8
7.8.1
Table 23.
Symbol VDR
Memory characteristics
SRAM characteristics
SRAM and hardware registers
Parameter Supply voltage for data retention(1) Conditions TA= 85C (worst case) Min 1.1 Typ Max Unit V
1. Guaranteed by characterization, not tested in production.
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Electrical characteristics
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7.8.2
Note:
Flash memory characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 C unless otherwise specified. Flash read access for sequential addresses is 0 wait states at 96 MHz. Flash read access for non-sequential accesses requires 2 wait states when FMI clock is above 66 MHz. See STR91xF Flash Programming Manual for more information.
Table 24.
Flash memory program/erase characteristics
Value Parameter Test Conditions Typ(1) 8 4 700 1300 300 3700 1900 250 500 60 Half word (16 bits) 8 Typ after 100K W/E cycles(1) 9 4.5 750 1400 320 4700 2000 260 520 62 9 Unit Max 11.5 6 950 1800 450 5100 2550 320 640 80 11 s s ms ms ms ms ms ms ms ms s
Primary Bank (512 Kbytes) Bank erase Primary Bank (256 Kbytes) Secondary Bank (32 Kbytes) Of Primary Bank (64 Kbytes) Sector erase Of Secondary Bank (8 Kbytes) Primary Bank (512 Kbytes) Bank program Primary Bank (256 Kbytes) Secondary Bank (32 Kbytes) Of Primary Bank (64 Kbytes) Sector program Of Secondary Bank (8 Kbytes) Word program
1. VDD = 1.8V, VDDQ = 3.3V, TA = 25C.
Table 25.
Flash memory endurance
Value Test Conditions Min Typ Max cycles years Per word 100K 20 Unit
Parameter Program/erase cycles Data retention
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Electrical characteristics
7.9
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
7.9.1
Functional EMS (electro magnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs).
ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD, VDDQ and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. Table 26.
Symbol
EMS data
Parameter Voltage limits to be applied on any I/O pin to induce a functional disturbance Fast transient voltage burst limits to be applied through 100pF on VDD and VDDQ pins to induce a functional disturbance Conditions VDD=1.8V, VDDQ=3.3V, TA=+25C, fOSC/fCPUCLK =4 MHz/96MHz PLL VDD=1.8V, VDDQ=3.3V, TA=+25C, fOSC/fCPUCLK =4 MHz/96 MHz PLL conforms to IEC 1000-4-4 Severity/ Criteria(1) 1B kV 4A Unit
VFESD
VFFTB
1. Data based on characterization results, not tested in production.
7.9.2
Electro magnetic interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin.
Table 27.
Symbo l
EMI data
Monitored Frequency Band Max vs. [fOSC/fCPUCLK] Unit 24 MHz / 48 MHz(1) 14 18 18 4 24 MHz / 96 MHz(1) 10 19 22 4 dBV
Parameter
Conditions
SEMI
Peak level
VDDQ=3.3V, VDD=1.8V, TA=+25C, LQFP128 package(2) conforming to SAE J 1752/3
0.1MHz to 30 MHz 30 MHz to 130 MHz 130 MHz to 1GHz SAE EMI Level
1. Data based on characterization results, not tested in production. 2. BGA and LQFP devices have similar EMI characteristics.
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Electrical characteristics
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7.9.3
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity.
7.9.4
Electro-static discharge (ESD)
Electro-Static Discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22-A114A/A115A standard. For more details, refer to the application note AN1181.
Table 28.
Symbol
ESD data
Ratings Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Charged Device Model) Conditions TA=+25C conforming to JESD22-A114 TA=+25C conforming to JESD22-C101 Class Maximum value (1) +/-2000 V II 1000 Unit
VESD(HBM)
2
VESD(CDM)
1. Data based on characterization results, not tested in production.
7.9.5
Static latch-up
Two complementary static tests are required on 10 parts to assess the latch-up performance.

A supply overvoltage (applied to each power supply pin) and A current injection (applied to each input, output and configurable I/O pin) are performed on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.
7.9.6
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the management of runaway conditions such as:

Corrupted program counter Unexpected reset Critical Data corruption (control registers...)
Prequalification trials:
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Electrical characteristics
Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
7.9.7
Electrical sensitivity
Table 29.
Symbol LU
Static latch-up data
Parameter Static latch-up class Conditions TA=+25C conforming to JESD78A Class (1) II class A
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard).
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Electrical characteristics
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7.10
Table 30.
Symbol
I/O characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 C unless otherwise specified. I/O characteristics
Value Parameter Test conditions Min General inputs(1) 2.0 0.8VDDQ VDDQ/2 0.8 0.2VDDQ VDDQ/2 0.4 VDDQ-0.7 VDDQ-0.7 VDDQ-0.1 0.4 0.4 0.1 V V V V Typ Max
(2)
Unit
VIH
Input High Level
RESET and TCK inputs(1) TAMPER_IN input General inputs(1)
(3)
VIL
Input Low Level
RESET and TCK inputs(1) TAMPER_IN input(3)
VHYS
Input Hysteresis Schmitt Trigger Output High Level High current pins
General inputs(4) I/O ports 3 and 6: Push-Pull, IOH = 8mA I/O ports 0,1,2,4,5,7,8,9: Push-Pull, IOH = 4mA IOH= -100 A I/O ports 3 and 6: Push-Pull, IOL = 8mA I/O ports 0,1,2,4,5,7,8,9: Push-Pull, IOL = 4mA IOL=100 A
VOH
Output High Level Standard current pins Output High Level JTAG JTDO pin Output Low Level High current pins
VOL
Output Low Level Standard current pins Output Low Level JTAG JTDO pin
1. Guaranteed by characterization, not tested in production. 2. Input pins are 5V tolerant, max input voltage is 5.5V 3. Guaranteed by design, not tested in production. 4. TAMPER_IN pin has no built-in hysteresis
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Electrical characteristics
7.11
External memory bus timings
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 C, CL= 30 pF unless otherwise specified. Table 31. EMI bus clock period
Symbol tBCLK Parameter(1) EMI Bus Clock period Value (2) 1 /(fHCLK x EMI_ratio)
1. The internal EMI Bus clock signal is available externally only on LFBGA144 packages (ball M8), and not available on LQFP packages. 2. EMI_ratio =1/ 2 by default (can be programmed to be 1 by setting the proper bits in the SCU_CLKCNTR register)
7.11.1
Asynchronous mode
Non Mux Write
Figure 17. Non-mux write timings
EMI_CSxn
EMI_A[15:0]
Address
EMI_D[7:0] tWAS tWDS EMI_BWR_WRLn
Data tWP tWCR
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Electrical characteristics Table 32.
Symbol Parameter Min tWCR tWAS tWDS tWP WRn to CSn inactive Write Address Setup Time Write Data Setup Time Write Pulse Width (tBCLK/2) - 2 ns
STR91xFAx32 STR91XFAX42 STR91xFAx44
EMI non-mux write operation
Value Max (tBCLK/2) + 2 ns ((WSTWEN + 1/2) x tBCLK) + 1 ns ((WSTWEN + 1/2) x tBCLK)
((WSTWEN + 1/2) x tBCLK ) - 2 ns ((WSTWEN + 1/2) x tBCLK ) - 5 ns
(WSTWR-WSTWEN + 1) x tBCLK - 1 ns (WSTWR-WSTWEN + 1) x tBCLK + 1.5 ns
Non-mux read
Figure 18. Non-mux bus read timings
EMI_CSxn
tRCR EMI_A [15:0] A ddress tRAH EMI_D[7:0] tRAS tRDS EMI_RDn tRP tRDH Data
Table 33.
Symbol
EMI read operation
Value Parameter Min Max 1.5 ns (WSTOEN) x tBCLK ((WSTRD-WSTOEN+1) x tBCLK)+ 2 ns Read to CSn inactive Read Address Setup Time Read Data Setup Time Read Data Hold Time Read Pulse Width
tRCR tRAS tRDS tRDH tRP
0 ((WSTOEN) x tBCLK)- 1.5 ns 12.5 0 ((WSTRD-WSTOEN+1) x tBCLK)0.5 ns
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Electrical characteristics
Mux write
Figure 19. Mux write diagram
EMI_CSxn
EMI_A LE tAW t W CR EMI_A [23:16] tAA S EMI_A D[15:0] A ddress tW AS EMI_WRLn EMI_WRHn t WP A ddress tAA H tW DS Data
Table 34.
Symbol
Mux write times
Value Parameter Min Max (tBCLK/2) + 2ns (WSTWEN + 1/2) x tBCLK + 2 ns
tWCR tWAS tWDS tWP tAW tAAS tAAH
WRn to CSn inactive Write Address Setup Time Write Data Setup Time Write Pulse Width ALE pulse width Address to ALE setup time Address to ALE hold time
(tBCLK/2) - 2ns (WSTWEN + 1/2) x tBCLK - 2.5 ns
((WSTWEN - ALE_LENGTH) x tBCLK) - 2 ((WSTWEN - ALE_LENGTH) x tBCLK) + 1 ns ns ((WSTWR-WSTWEN + 1) x tBCLK) - 1 ns (ALE_LENGTH x tBCLK )- 3.5 ns (ALE_LENGTH x tBCLK )- 3.5 ns (tBCLK/2) - 1 ns ((WSTWR-WSTWEN + 1) x tBCLK) + 1.5 ns (ALE_LENGTH x tBCLK ) (ALE_LENGTH x tBCLK ) (tBCLK/2) + 2 ns
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Electrical characteristics
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Mux read
Figure 20. Mux read diagram
EMI_CSxn
EMI_A LE t AW t RCR EMI_A [23:16] t AAS EMI_A D[15:0] A ddress tRA S EMI_RDn tRP A ddress tAAH Data tRDS t RDH
Table 35.
Symbol tRCR tRAS tRDS tRDH tRP tAW tAAS tAAH
Mux read times
Value Parameter Min Max Read to CSn 0 1.5 ns inactive Read Address Setup ((WSTOEN) x tBCLK) ((WSTOEN) x tBCLK)- 4 ns Time Read Data Setup 12 ns Time Read Data Hold 0 Time Read Pulse Width ((WSTRD-WSTOEN+1) x tBCLK) - 0.5 ns ((WSTRD-WSTOEN+1) x tBCLK) + 2.5 ns ALE pulse width (ALE_LENGTH x tBCLK) - 3.5 ns (ALE_LENGTH x tBCLK ) Address to ALE (ALE_LENGTH x tBCLK ) (ALE_LENGTH x tBCLK) - 3.5 ns setup time Address to ALE hold (tBCLK/2) + 2 ns (tBCLK/2)- 1 ns time
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Electrical characteristics
Page mode read
Figure 21. Page mode read diagram
CSx
EMI_RD
tRAS
A15-A2
tRCR
A15-A2
tADW
A1-A0 Addr 0 Addr 1 Addr 2 Addr 3
tRP
D0-D7 Data 0 Data 1 Data 2 Data 3
tRDS
tRDH
Table 36.
Symbol tRDH tRDS tADW tRAS tRP tRCR
Page mode read times
Value Parameter Min Read Data Hold Time Read Data Setup Time ALE pulse width Read Address Setup Time Read Pulse Width Read to CSn inactive 0 12 ns (tBCLK) - 1.5 ns ((WSTOEN) x tBCLK) ((WSTRD-WSTOEN+1) x tBCLK) 0 (tBCLK )+ 0.5 ns ((WSTOEN) x tBCLK) + 2.5 ns ((WSTRD-WSTOEN+1) x tBCLK) + 2 ns 1 ns Max
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7.11.2
Synchronous mode
Sync burst write
Figure 22. Sync burst write diagram
EMI_BCLK
EMI_ALE CS
EMI_WE EMI_UB EMI_LBN EMI_BAA EMI_WAIT AD15:0 D_OUT15:0 A15:0 Data 0 Data 1 Data 2 Data 3 Data n
EMI_BCLK EMI_ALE CS EMI_WE EMI_BAA A[15:0]
tD1
tD2
tDS
tDH DATA tWS
D_IN[15:0]
EMI_WAIT
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STR91xFAx32 STR91XFAX42 STR91xFAx44 Table 37. Sync burst write times
Electrical characteristics
Value Symbol tD1BAA tD2BAA tD1ALE tD2ALE tD1WR tD2WR tD1A tD2A tD1CS tD2CS tWS tDS tDH Parameter Min BAA tD1 BAA tD2 ALE tD1 ALE tD2 RD tD1 RD tD2 Address tD1 Address tD2 CS tD1 CS tD2 WAIT setup time Data setup time Data hold time 0 0.5 ns 1 ns (tBCLK/2) -0.5 ns 0 0.5 ns 1.5 ns 2ns 0.5ns 1 ns 3 ns (tBCLK/2) -3.5 ns (tBCLK/2) - 1 ns Max 2 ns 2.5 ns 3.5 ns (tBCLK/2) + 3.5 ns 2ns 2.5 ns 4 ns 4.5 ns 3 ns 3.5 ns 6 ns (tBCLK/2)+ 0.5 ns (tBCLK/2)+3.5 ns
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Electrical characteristics
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Sync burst read
Figure 23. Sync burst read diagram
EMI_BCLK EMI_ALE CSxn EMI_RDn EMI_BAAn A[15:0] tD1 tD2
tDS D_IN[15:0]
tDH
DATA tWS
EMI_WAITn
Table 38.
Sync burst read times
Value Parameter Min Max 2 ns 2.5 ns 3.5 ns (tBCLK/2)+3 ns 2 ns 2.5 ns 4 ns 3.5 ns 3 ns 3.5 ns 4 ns BAA tD1 BAA tD2 ALE tD1 ALE tD2 RD tD1 RD tD2 Address tD1 Address tD2 CS tD1 CS tD2 WAIT set up time Data setup time Data hold time 0 ns 0.5ns 1 ns (tBCLK/2)+0.5 ns 0 0.5 ns 2 ns 2.5 ns 0.5 ns 1 ns 1 ns 4.5 ns 0
Symbol tD1BAA tD2BAA tD1ALE tD2ALE tD1RD tD2RD tD1A tD2A tD1CS tD2CS tWS tDS tDH
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Electrical characteristics
7.12
7.12.1
Communication interface electrical characteristics
10/100 Ethernet MAC electrical characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 C unless otherwise specified.
Ethernet MII interface timings
Figure 24. MII_RX_CLK and MII_TX_CLK timing diagram
3 MII_RX_TCLK, MII_TX_CLK 2 4 1 4
Table 39.
Symbol 1 2 3 4
MII_RX_CLK and MII_TX_CLK timing table
Value Parameter Cycle time Pulse duration HIGH Pulse duration LOW Transition time Symbol Min tc(CLK) tHIGH(CLK) tLOW(CLK) tt(CLK) 40 40% 40% 60% 60% 1 ns Max ns Unit
Figure 25. MDC timing diagram
3 MDC 2 4 1 4
Table 40.
Symbol 1 2 3 4
MDC timing table
Value Parameter Cycle time Pulse duration HIGH Pulse duration LOW Transition time Symbol Min tc(MDC) tHIGH(MDC) tLOW(MDC) tt(MDC) 266 40% 40% 60% 60% 1 ns Max ns Unit
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Ethernet MII management timings
Figure 26. Ethernet MII management timing diagram
MDC 1 MDIO output MDIO input
2
3
Table 41.
Symbol
Ethernet MII management timing table
Value Parameter MDIO delay from rising edge of MDC MDIO setup time to rising edge of MDC MDIO hold time from rising edge of MDC Symbol Min Max 2.83 2.70 -2.03 ns ns ns Unit
1 2 3
tc(MDIO) Tsu (MDIO) Th (MDIO)
Ethernet MII transmit timings
Figure 27. Ethernet MII transmit timing diagram
MII_TX_CLK
1 3 4 5 8 7 6 2
MII_TX_EN MII_CRS MII_COL MII_TXD
Table 42.
Symbol
Ethernet MII transmit timing table
Value Parameter MII_TX_CLK high to MII_TX_EN valid MII_TX_CLK high to MII_TX_EN invalid MII_CRS valid to MII_TX_CLK high MII_TX_CLK high to MII_CRS invalid MII_COL valid to MII_TX_CLK high Symbol Min Max 4.20 4.86 0.61 0.00 0.81 ns ns ns ns ns Unit
1 2 3 4 5
tVAL(MII_TX_EN) Tinval(MII_TX_EN) Tsu(MII_CRS) Th(MII_CRS) Tsu(MII_COL)
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STR91xFAx32 STR91XFAX42 STR91xFAx44 Table 42.
Symbol
Electrical characteristics
Ethernet MII transmit timing table
Value Parameter MII_TX_CLK high to MII_COL invalid MII_TX_CLK high to MII_TXD valid MII_TXCLK high to MII_TXD invalid Symbol Min Max ns 5.02 5.02 ns ns Unit
6 7 8
Th(MII_COL) tVAL(MII_TXD) Tinval(MII_TXD
0.00
Ethernet MII receive timings
Figure 28. Ethernet MII receive timing diagram
MII_RX_CLK
1 2
MII_RXD MII_RX_DV MII_RX_ER
Table 43.
Symbol
Ethernet MII receive timing table
Value Parameter MII_RXD valid to MII_RX_CLK high MII_RX_CLK high to MII_RXD invalid Symbol Min Max ns ns Unit
1 2
Tsu(MII_RXD) Th(MII_RXD)
0.81 0.00
7.12.2
USB electrical interface characteristics
USB 2.0 Compliant in Full Speed Mode
7.12.3
CAN interface electrical characteristics
Conforms to CAN 2.0B protocol specification
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7.12.4
I2C electrical characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 C unless otherwise specified. Table 44.
Symbol
I2C electrical characteristics
Standard I2C Parameter Min Max Min 1.3 Max ms Bus free time between a STOP and START condition Hold time START condition. After this period, the first clock pulse is generated(1) LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time(2) Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Capacitive load for each bus line 4.0 400 Fast I2C Unit
tBUF
4.7
tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO Cb
4.0 4.7 4.0 4.7 0 250 1000 300
0.6 1.3 0.6 0.6 0 100 20+0.1Cb
(3)
s s s s ns ns 300 300 ns ns s 400 pF
20+0.1Cb
(3)
0.6
1. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal 2. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 3. Cb = total capacitance of one bus line in pF
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Electrical characteristics
7.12.5
SPI electrical characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 C unless otherwise specified. Table 45.
Symbol
SPI electrical characteristics
Value Parameter Test Conditions Typ Max 24 MHz Slave SPI clock rise and fall times SS setup time SS hold time SCLK high and low time Data input setup time Data input hold time Data output access time Data output disable time Data output valid time Data output hold time Data output valid time Data output hold time 50pF load Slave Slave Master Slave Master Slave Master Slave Slave Slave Slave (after enable edge) Master (before capture edge) 1 1 1 5 6 6 6 6 0 0.25 0.25 0.1 4 V/ns Master SPI clock frequency Unit
fSCLK 1/tc(SCLK) tr(SCLK) tf(SCLK) tsu(SS) th(SS) tw(SCLKH) tw(SCLKL) tsu(MI) tsu(SI) th(MI) th(SI) ta(SO) tdis(SO) tv(SO) th(SO) tv(MO) th(MO)
tPCLK
Figure 29. SPI slave timing diagram with CPHA=0
NSS INPUT tsu(NSS) SCLK INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) MISO OUTPUT tsu(SI) tw(SCLKH) tw(SCLKL) tv(SO) th(SO) tr(SCLK) tf(SCLK)
LSB OUT
tc(SCLK)
th(NSS)
tdis(SO)
MSB OUT
BIT6 OUT
th(SI)
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
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Electrical characteristics
STR91xFAx32 STR91XFAX42 STR91xFAx44
Figure 30. SPI slave timing diagram with CPHA=1
NSS INPUT tsu(NSS) SCLK INPUT CPHA=1 CPOL=0 CPHA=1 CPOL=1 ta(SO) tw(SCLKH) tw(SCLKL) tv(SO) th(SO) tr(SCLK) tf(SCLK)
LSB OUT
tc(SCLK)
th(NSS)
tdis(SO)
MISO OUTPUT
HZ
MSB OUT
BIT6 OUT
tsu(SI)
th(SI)
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
Figure 31. SPI master timing diagram
NSS INPUT
tc(SCLK) CPHA=0 CPOL=0 SCLK IOUTPUT CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCLKH) tw(SCLKL) tsu(MI) MISO INPUT tv(MO) th(MI) tr(SCLK) tf(SCLK)
MSB IN
BIT6 IN
LSB IN
th(MO)
MOSI OUTPUT
MSB OUT
BIT6 OUT
LSB OUT
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Electrical characteristics
7.13
Table 46.
Symbol VAIN RES NCH fADC
ADC electrical characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 C unless otherwise specified. General ADC electrical characteristics
Parameter(1) Input Voltage Range Resolution Number of Input Channels ADC Clock Frequency Test Conditions Value Unit Min 0 Typ Max AVREF 10 8 25 500 1 15 5
(3) (4) (3) (3) (3) (3)
V Bits N MHz ms ms s pF
tPOR(ADC) POR bit set to Standby mode tck_off(ADC) ADC clock disabled before conversion (2) tSTAB CIN ED EL EO EG ET IADC Stabilization time Input Capacitance Differential Non-Linearity Integral Non-Linearity Offset Error Gain Error Total Unadjusted Error Power Consumption
1 3 3 0.5 4 4.6
3 6 6 2 6
LSB(5) LSB(5) LSB(5) LSB(5) LSB(5) mA
1. Guaranteed by design, not tested in production. 2. The ADC clock can be disabled by setting the ADC bit in the SCU_PCGR1 register or by setting the ACG bit in the SCU_GPIOANA register (for Rev H only) 3. Conditions: AVSS = 0 V, AVDD = 3.3 V fADC = 25 MHz. 4. The A/D is monotonic, there are no missing codes. 5. 1 LSB = (AVDD - AVSS)/1024
Table 47.
Symbol
ADC conversion time (silicon Rev H)
Parameter(1) (2) Test Conditions Value Unit Min 1*16/fADC fADC = 24 MHz Single mode throughput rate (3) Continuous mode conversion time(4) fADC = 24 MHz Continuous mode throughput rate fADC = 24 MHz fADC = 24 MHz 1*16/fADC 0.66 1500 0.66 Typ Max 2*16/fADC 1.33 750 ksps s s ksps s
tCONV(S] TR(S) tCONV(C] TR(C)
Single mode conversion time
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Electrical characteristics Table 47.
Symbol
STR91xFAx32 STR91XFAX42 STR91xFAx44
ADC conversion time (silicon Rev H)
Parameter(1) (2) Test Conditions Value Unit Min Typ 1*16/fADC fADC = 24 MHz Fast trigger mode throughput rate
(6)
Max s s 1200 ksps
tCONV(FT] TR(FT)
Fast trigger mode conversion time(5) fADC = 24 MHz 100
0.66
1. Guaranteed by design, not tested in production. 2. Parameters in this table apply to devices with silicon Rev H and higher. Refer to Table 6 for device rev identification in OTP memory and to Section 8: Device marking. 3. Value obtained from conversions started by trigger in single mode 4. All sucessive conversions in continuous and scan modes. 5. Conversion started by trigger when automatic clock gated mode enabled. Fast trigger mode is available only in devices with silicon Rev H and higher. 6. Value obtained from conversions started by fast trigger in single mode
Table 48.
Symbol
ADC conversion time (silicon Rev G and lower)
Parameter(1) (2) Test Conditions Value Unit Min 2*16/fADC fADC = 24 MHz Single mode throughput rate (3) Continuous mode conversion time(4) fADC = 24 MHz Continuous mode throughput rate fADC = 24 MHz fADC = 24 MHz 1*16/fADC 0.66 1500 1.33 Typ Max 3*16/fADC 2 500 ksps s s ksps s
tCONV(S] TR(S) tCONV(C] TR(C)
Single mode conversion time
1. Guaranteed by design, not tested in production. 2. Parameters in this table apply to devices with silicon Rev G and lower. Refer to Table 6 for device rev identification in OTP memory and to Section 8: Device marking. 3. Value obtained on conversions started by trigger in single mode 4. All sucessive conversions in continuous and scan modes.
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STR91xFAx32 STR91XFAX42 STR91xFAx44 Figure 32. ADC conversion characteristics Digital Result
1023 1022 1021
1LSB IDEAL V -V DDA SSA = ----------------------------------------
Electrical characteristics
EG
(1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line
1024
(2) ET 7 6 5 4 3 2 1 0 1 AVSS 2 3 4 1 LSBIDEAL EO EL ED (3) (1)
ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.
Vin
5 6 7 1021 1022 1023 1024 AVDD
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Device marking
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8
Device marking
Figure 34. Device marking for revision G LFBGA144 packages
Figure 33. Device marking for revision G LQFP80 and LQFP128 packages
Figure 35. Device marking for revision H LQFP80 and LQFP128 packages
Figure 36. Device marking for revision H LFBGA144 packages
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Package mechanical data
9
Package mechanical data
Figure 37. 80-Pin low profile quad flat package (LQFP80)
SEATING PLANE C
A A2
mm Dim. Min
0.25 mm GAGE PLANE
inches1) Min Typ Max 0.0630
Typ Max 1.60
A1
A A1 A2 b c D D2 E
c
0.05 0.10 0.15 0.0020 0.0039 0.0059 1.35 1.40 1.45 0.0531 0.0551 0.0571 0.17 0.22 0.27 0.0067 0.0087 0.0106 0.09 0.20 0.0035 0.0079 13.80 14.00 14.20 0.5433 0.5512 0.5591 9.50 0.3740
ccc
C D
A1
b
k
D1 D2
60 41
L L1
D1 11.90 12.00 12.10 04685 0.4724 0.4764
40
61
13.80 14.00 14.20 0.5433 0.5512 0.5591 9.50 0.50 1.00 0d 7d 0.08 0d 0.3740 0.0197 0.039 7d 0.0031
b E2 E1 E
E1 11.90 12.00 12.10 04685 0.4724 0.4764 E2 e L L1
80 21
0.45 0.60 0.75 0.0177 0.0236 0.0295
k ddd
1
20
e PIN 1 IDENTIFICATION
Number of Pins
N
1Values
80
in inches are converted from mm and rounded to 4 decimal digits.
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Package mechanical data
STR91xFAx32 STR91XFAX42 STR91xFAx44
Figure 38. 128-Pin low profile quad flat package (LQFP128)
SEATING PLANE C
mm Dim.
A A2
inches1] Min Typ Max 0.0630 0.0059
Min
0.25 mm GAGE PLANE
Typ Max 1.60
A1
A A1 A2 b c D D3 E 0.05
c
0.15 0.0020
ccc
C D
b
1.35 1.40 1.45 0.0531 0.0551 0.0571 0.13 0.18 0.23 0.0051 0.0071 0.0091 0.09 0.20 0.0035 0.0079 15.80 16.00 16.20 0.6220 0.6299 0.6378 12.40 0.4882
k
A1
D1 D3
96 65
L L1
D1 13.80 14.00 14.20 0.5433 0.5512 0.5591
64
97
15.80 16.00 16.20 0.6220 0.6299 0.6378 12.40 0.40 1.00 0d 3.5d 7d 0.08 0d 0.4882 0.0157 0.0394 3.5d 7d 0.0031
b E3 E1 E
E1 13.80 14.00 14.20 0.5433 0.5512 0.5591 E3 e L
128 33
0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 k ccc
1
32
e PIN 1 IDENTIFICATION
Number of Pins
N
1Values
128 in inches are converted from mm and rounded to 4 decimal digits.
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Package mechanical data
Figure 39. 144-ball low profile fine pitch ball grid array package (LFBGA144)
mm Dim. Min
A A1 A2 b D D1 E E1 e F ddd eee fff 9.85 0.35 9.85 1.21 0.21 1.085 0.40 0.45
inches1) Max
1.70
Typ
Min
0.0476 0.0083
Typ
Max
0.0669
0.0427 0.0138 0.0157 0.0177
10.00 10.15 0.3878 0.3937 0.3996 8.80 0.3465
10.00 10.15 0.3878 0.3937 0.3996 8.80 0.80 0.60 0.10 0.15 0.08 Number of Pins 0.3465 0.0315 0.0236 0.0039 0.0059 0.0031
N
1
144
Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 40. Recommended PCB Design rules (0.80/0.75mm pitch BGA)
Dpad
0.37 mm 0.52 mm typ. (depends on solder Dsm mask registration tolerance Solder paste 0.37 mm aperture diameter - Non solder mask defined pads are recommended - 4 to 6 mils screen print
Dpad Dsm
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Package mechanical data
STR91xFAx32 STR91XFAX42 STR91xFAx44
9.1
Soldering information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label (JEDEC 020C). ECOPACK is an ST trademark. ECOPACK(R) specifications are available at www.st.com.
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Package mechanical data
9.2
Thermal characteristics
The average chip-junction temperature, TJ must never exceed 125 C. The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using the following equation: TJ = TA + (PD x JA)(1) Where: - - - - TA is the Ambient Temperature in C, JA is the Package Junction-to-Ambient Thermal Resistance, in C/W, PD is the sum of PINT and PI/O (PD = PINT + PI/O), PINT is the product of IDD and VDD, expressed in Watts. This is the Chip Internal Power.
PI/O represents the Power Dissipation on Input and Output Pins; Most of the time for the applications PI/O < PINT and may be neglected. On the other hand, PI/O may be significant if the device is configured to drive continuously external modules and/or memories. The worst case PINT of the STR91xFA is 500mW (IDD x VDD, or 250mA x 2.0V). An approximate relationship between PD and TJ (if PI/O is neglected) is given by: PD = K / (TJ + 273C) (2) Therefore (solving equations 1 and 2): K = PD x (TA + 273C) + JA x PD2(3) where: - K is a constant for the particular part, which may be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations (1) and (2) iteratively for any value of TA.
Table 49.
Symbol JA JA JA
Thermal characteristics
Parameter Thermal Resistance Junction-Ambient LQFP 80 - 12 x 12 mm / 0.5 mm pitch Thermal Resistance Junction-Ambient LQFP128 - 14 x 14 mm / 0.4 mm pitch Thermal Resistance Junction-Ambient LFBGA 144 - 10 x 10 x 1.7mm Value 41.5 38 36.5 Unit C/W C/W C/W
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Ordering information
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10
Ordering information
Table 50. Ordering information
Flash KB 256+32 256+32 256+32 256+32 512+32 256+32 512+32 256+32 256+32 512+32 256+32 512+32 RAM KB 64 64 64 96 USB, CAN, 40 I/Os STR911FAM44X6 STR911FAW42X6 STR911FAW44X6 STR912FAW32X6 STR912FAW42X6 STR912FAW44X6 STR912FAZ42H6 STR912FAZ44H6 96 96 USB, CAN, EMI, 80 I/Os 96 64 96 96 96 96 Ethernet, USB, CAN, EMI, 80 I/Os Ethernet, USB, CAN, EMI, 80 I/Os Major Peripherals CAN, 40 I/Os CAN, EMI, 80 I/Os CAN, EMI, 80 I/Os Package LQFP80, 12x12 mm LQFP128, 14x14 mm LFBGA144 10 x 10 x 1.7 LQFP80, 12x12mm
Part Number STR910FAM32X6 STR910FAW32X6 STR910FAZ32H6 STR911FAM42X6
LQFP128, 14x14mm LQFP128
LQFP128
Ethernet, USB, CAN, EMI, 80 I/Os
LFBGA144 10 x 10 x 1.7
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STR91xFAx32 STR91XFAX42 STR91xFAx44 Table 51.
Example: Family ARM9 Microcontroller Family
Ordering information
Ordering information scheme
STR9 1 2 F A W 4 4 X 6 T
Series 1 = STR9 Series 1 Feature set 0 = CAN, UART, IrDA, I2C, SSP 1 = USB, CAN, UART, IrDA, I2C, SSP 2 = USB, CAN, UART, IrDA, I2C, SSP, ETHERNET Memory type F = Flash Revision at product level A = Revison A
No. of pins M = 80 W = 128 Z = 144
SRAM size 3 = 64K 4 = 96K Primary Memory Size 2 = 256K 4 = 512K Package X = plastic LQFP H = LFBGA Temperature Range 6 = -40 to 85C Shipping Option T = Tape & Reel Packing For a list of available options (e.g. speed, package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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Revision history
STR91xFAx32 STR91XFAX42 STR91xFAx44
11
Revision history
Table 52.
Date 09-May-2007
Document revision history
Revision 1 Initial release Updated Standby current in Table 11: Current characteristics on page 59 Added Section 7.1: Parameter conditions on page 57 Added Section 7.7.2: X1_CPU external clock source on page 65 Updated Section 7.11: External memory bus timings on page 73 Added Figure 14: LVD reset delay case 3 on page 62 Added Table 47 and Table 48 in ADC characteristics section Added min/max values for E, D, E1, D1 in Figure 37 on page 91 Changes
26-Nov-2007
2
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